SB16C1058_Data Sheet_EN

SB16C1058
OCTAL UART WITH 256-BYTE FIFO
JULY 2013 REV 1.04
62
t
sim
Propagation delay time, RI# ↑ to INT ↓
12
ns
† The internal address strobe is always in active state.
‡ In the FIFO mode, td1= xxns (min) between reads of the FIFO and the status register.
t
t
ra
t
IOR#
t
CSx#
t
t
t
A[2:0]
VALID DATA
hz
VALID ADDRESS
D[7:0]
rvd
rc
IOW#
rd
rcs
ar
t
csr
t
ACTIVE
frc
Figure 10: Read Cycle Timing
fwc
wr
t
dh
ACTIVE
t t
wa
t
t
D[7:0]
t
wc
t
A[2:0]
t
VALID DATA
t
VALID ADDRESS
CSx#
aw
wcscsw
ds
IOW#
IOR#
Figure 11: Write Cycle Timing