SB16C1058_Data Sheet_EN

SB16C1058
OCTAL UART WITH 256-BYTE FIFO
JULY 2013 REV 1.04
50
Table 25: SB16C1058 Reset Conditions
Registers
Reset State
Page 0
RBR
[7:0] = ‘XXXX_XXXX’
IER
[7:0] = ‘0000_0000’
FCR
[7:0] = ‘0000_0000’
ISR
[7:0] = ‘0000_0001’
LCR
[7:0] = ‘0000_0000’
MCR
[7:0] = ‘0000_0000’
LSR
[7:0] = ‘0110_0000’
MSR
[7:4] = ‘0000’
[3:0] = Logic levels of the inputs inverted
SPR
[7:0] = ‘0000_0000’
Page 1
DLL
[7:0] = ‘1111_1111’
DLM
[7:0] = ‘1111_1111’
Page 2
GICR
[7:0] = ‘0000_0000’
GISR
[7:0] = ‘0000_0000’
TCR
[7:0] = ‘0000_0000’
RCR
[7:0] = ‘0000_0000’
FSR
[7:0] = ‘0000_0000’
Page 3
PSR
[7:0] = ‘0000_0000’
ATR
[7:0] = ‘1010_0000’
EFR
[7:0] = ‘0000_0000’
XON1
[7:0] = ‘0000_0000’
XON2
[7:0] = ‘0000_0000’
XOFF1
[7:0] = ‘0000_0000’
XOFF2
[7:0] = ‘0000_0000’
Page 4
AFR
[7:0] = ‘0000_0000’
XRCR
[7:0] = ‘0000_0000’
TTR
[7:0] = ‘1000_0000’
RTR
[7:0] = ‘1000_0000’
FUR
[7:0] = ‘0000_0000’
FLR
[7:0] = ‘0000_0000’
Output Signals
Reset State
TXD, RTS#, DTR#
Logic 1
TXRDY#, TXEN, RXEN#
Logic 0
RXRDY#
Logic 1
INT
Tri-State Condition = INTSEL is open or low state
Logic 0 = INTSEL is high state