SB16C1058_Data Sheet_EN

SB16C1058
OCTAL UART WITH 256-BYTE FIFO
JULY 2013 REV 1.04
37
7.5 FIFO Control Register (FCR, Page 0)
FCR is used for enabling the FIFOs, clearing the FIFOs, setting transmit/receive FIFO
trigger level, and selecting the DMA modes. Table 12 shows FCR bit settings.
Table 12: FIFO Control Register Description
Bit
Symbol
Description
7:6
FCR[7:6]
RX FIFO Trigger Level Select
00 : 8 characters (default)
01 : 16 characters
10 : 56 characters
11 : 60 characters
Flow Control Upper Threshold Level Select
00 : 8 characters (default)
01 : 16 characters
10 : 56 characters
11 : 60 characters
5:4
FCR[5:4]
TX FIFO Trigger Level Select
00 : 8 characters (default)
01 : 16 characters
10 : 32 characters
11 : 56 characters
Flow Control Lower Threshold Level Select
00 : 0 character (default)
01 : 8 characters
10 : 16 characters
11 : 56 characters
FCR[5:4] can only be modified and enabled when EFR[4] is set.
3
FCR[3]
DMA Mode Select
0 : Set DMA mode 0 (default)
1 : Set DMA mode 1
2
FCR[2]
TX FIFO Reset
0 : No TX FIFO reset (default)
1 : Reset TX FIFO pointers and TX FIFO level counter logic.
This bit will return to ‘0’ after resetting FIFO.
1
FCR[1]
RX FIFO Reset
0 : No RX FIFO reset (default)
1 : Reset RX FIFO pointers and RX FIFO level counter logic.
This bit will return to ‘0’ after resetting FIFO.
0
FCR[0]
FIFO enable
0 : Disable the TX and RX FIFO (default).
1 : Enable the TX and RX FIFO