SB16C1058_Data Sheet_EN

ManualsBrandsSystemBase ManualsElectronic ComponentsOctal UART with 256 Byte TX/RX FIFO, 80-pin TQFP - 60pcs Bundle

SB16C1058

OCTAL UART WITH 256-BYTE FIFO

JULY 2013 REV 1.04

33

Table 9: Internal Registers Description

Addr.

A[2:0]

Reg.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page 0 Registers

0h

THR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0h

RBR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1h

IER

0/NCTS

Interrupt

Enable

0/NRTS

Interrupt

Enable

0/Xoff

Interrupt

Enable

0/Sleep

Mode

Enable

Modem

Status

Interrupt

Enable

Receive

Line

Status

Interrupt

Enable

THR

Empty

Interrupt

Enable

Receive

Data

Available

Interrupt

Enable

2h

ISR

FCR[0]/

256-TX

FIFO

Empty

FCR[0]/

256-RX

FIFO

Full

Interrupt

Priority

Bit 5

Interrupt

Priority

Bit 4

Interrupt

Priority

Bit 3

Interrupt

Priority

Bit 2

Interrupt

Priority

Bit 1

Interrupt

Priority

Bit 0

2h

FCR

RX

Trigger

Level

(MSB)

RX

Trigger

Level

(LSB)

0/TX

Trigger

Level

(MSB)

0/TX

Trigger

Level

(LSB)

DMA

Mode

Select

TX FIFO

Reset

RX

FIFO

Reset

FIFO

Enable

3h

LCR

Divisor

Enable

Set

TX Brake

Set

Parity

Parity

Type

Select

Parity

Enable

Stop

Bits

Word

Length

Bit 1

Word

Length

Bit 0

4h

MCR

Clock

Select

Page 2

Select/Xoff

Re-Transmit

Access

Enable

0/Xon

Any

0/Loop

Back

OUT2/

INTx

Enable

OUT1/

Xoff Re-

Transmit

Enable

NRTS

NDTR

5h

LSR

RX FIFO

Data

Error

THR &

TSR

Empty

THR

Empty

Receive

Break

Framing

Error

Parity

Error

Overrun

Error

Receive

Data

Ready

6h

MSR

NDCD

NRI

NDSR

NCTS

∆NDCD

∆NRI

∆NDSR

∆NCTS

7h

SCR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page 1 Registers

0h

DLL

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1h

DLM

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Page 2 Registers

1h

GICR

CH7

Interrupt

Mask

CH6

Interrupt

Mask

CH5

Interrupt

Mask

CH4

Interrupt

Mask

CH3

Interrupt

Mask

CH2

Interrupt

Mask

CH1

Interrupt

Mask

CH0

Interrupt

Mask

2h

GISR

CH 7

Interrupt

Status

CH 6

Interrupt

Status

CH 5

Interrupt

Status

CH 4

Interrupt

Status

CH 3

Interrupt

Status

CH 2

Interrupt

Status

CH 1

Interrupt

Status

CH 0

Interrupt

Status

5h

TCR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

6h

RCR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

7h

FSR

0

0

TX HW

Flow

Control

Status

TX SW

Flow

Control

Status

0

0

RX HW

Flow

Control

Status

RX SW

Flow

Control

Status