SB16C1054PCI_Data Sheet_EN

SB16C1054PCI
PCI Target Interface Controller
with Quad-UART
JULY 2013 REV 1.04
72
16. Timing Specification
16.1 PCI BUS Timing Specifications
Symbol
Parameter
66MHz
33MHz
Units
Min
Max
Min
Max
T
val
CLK to signal valid delay - bused signals
2
6
2
11
ns
T
val
(ptp)
CLK to signal valid delay - point to point
signals
2
6
2
12
ns
T
on
float to active delay
2
2
ns
T
off
active to float delay
14
28
ns
T
su
input setup time to CLK – bused signals
3
7
ns
T
su
(ptp)
input setup time to CLK - point to point
signals
5
10,
12
ns
T
h
Input hold time from CLK
0
0
ns
T
rst
Reset active time after power stable
1
1
ms
T
rst-clk
Reset active time after CLK stable
100
100
us
T
rst-off
Reset active to output float delay
40
40
ns
T
rhfa
RST# high to first configuration access
2
2
clocks
T
rhff
RST# high to first FRAME# assertion
5
5
clocks
Table 16–1: PCI Bus Timing Specifications
T_val
V_test
V_tfall
T_val
V_trise
T_on
T_off
CLK
OUTPUT
DELAY
Tri-State
OUTPUT
OUTPUT
DELAY
V_Tl
V_Th
Figure 16-1: Output Timing Measurement Conditions