SB16C1054PCI_Data Sheet_EN

SB16C1054PCI
PCI Target Interface Controller
with Quad-UART
JULY 2013 REV 1.04
65
Table 13–16: SB16C1050 Reset Conditions
Registers
Reset State
Page 0
RBR
[7:0] = XXXX_XXXXb
IER
[7:0] = 0000_0000b
FCR
[7:0] = 0000_0000b
ISR
[7:0] = 0000_0001b
LCR
[7:0] = 0000_0000b
MCR
[7:0] = 0000_0000b
LSR
[7:0] = 0110_0000b
MSR
[7:4] = 0000b
[3:0] = Logic levels of the inputs inverted
SPR
[7:0] = 0000_0000b
Page 1
DLL
[7:0] = 1111_1111b
DLM
[7:0] = 1111_1111b
Page 2
TCR
[7:0] = 0000_0000b
RCR
[7:0] = 0000_0000b
FSR
[7:0] = 0000_0000b
Page 3
PSR
[7:0] = 0000_0000b
ATR
[7:0] = 1010_0000b
EFR
[7:0] = 0000_0000b
XON1
[7:0] = 0000_0000b
XON2
[7:0] = 0000_0000b
XOFF1
[7:0] = 0000_0000b
XOFF2
[7:0] = 0000_0000b
Page 4
AFR
[7:0] = 0000_0000b
XRCR
[7:0] = 0000_0000b
TTR
[7:0] = 1000_0000b
RTR
[7:0] = 1000_0000b
FUR
[7:0] = 0000_0000b
FLR
[7:0] = 0000_0000b
Output Signals
Reset State
TXD, RTS#, DTR#
Logic 1
TXEN, RXEN#
Logic 0
INT
Tri-State Condition = INTSEL is open or low state
Logic 0 = INTSEL is high state