SB16C1054PCI_Data Sheet_EN

SB16C1054PCI
PCI Target Interface Controller
with Quad-UART
JULY 2013 REV 1.04
62
13.17 Enhanced Feature Register (EFR, Page 3)
EFR enables or disables the enhanced features of the UART. Table 13–13 shows EFR
bit settings.
Table 13–13: Enhanced Feature Register Description
Bit
Symbol
Description
7
EFR[7]
Auto-CTS Flow Control Enable:
0b: Auto-CTS flow control is disabled (default).
1b: Auto-CTS flow control is enabled. Transmission stops
when CTS# pin is inputted 1b. Transmission resumes
when CTS# pin is inputted 0b.
6
EFR[6]
Auto-RTS Flow Control Enable:
0b: Auto-RTS flow control is disabled (default).
1b: Auto-RTS flow control is enabled. The RTS# pin outputs
1b when data in RX FIFO fill above the FUR. RTS# pin
outputs 0b when data in RX FIFO fall below the FLR.
5
EFR[5]
Special Character Detect:
0b: Special character detect disabled (default).
1b: Special character detect enabled. The UART compares
each incoming character with data in Xoff2 register. If a
match occurs, the received data is transferred to RX FIFO
and ISR[4] is set to 1b to indicate that a special character
has been detected.
4
EFR[4]
Enhanced Function Bits Enable:
0b: Disables enhanced functions and writing to IER[7:4],
FCR[5:4], MCR[7:5].
1b: Enables enhanced function IER[7:4], FCR[5:4], and MCR
[7:5] can be modified, i.e., this bit is therefore a write
enable.
3:0
EFR[3:0]
Software Flow Control Select:
Single character and dual sequential characters software flow
control is supported. Combinations of software flow control
can be selected by programming these bits. See Table 12–1
“Software flow control options (EFR[3:0])” on page 45.