SB16C1054PCI_Data Sheet_EN

SB16C1054PCI
PCI Target Interface Controller
with Quad-UART
JULY 2013 REV 1.04
61
13.16 Auto Toggle Control Register (ATR, Page 3)
ATR controls the signals for controlling input/output signals when using Line Interface
as RS422 or RS485, so eliminates additional glue logic outside. Ta ble 13–12 shows
ATR bit settings.
Table 13–12: Auto Toggle Control Register Description
Bit
Symbol
Description
7
ATR[7]
RXEN# Polarity Select:
0b: Asserted output of RXEN# is 0b.
1b: Asserted output of RXEN# is 1b. (default)
6
ATR[6]
RXEN# Control Mode Select:
Only when ATR[1:0] is 11b;
0b: RXEN# is outputted as same as ATR[7], irrespective of
TXD signal. (default)
1b: RXEN# is outputted as same as ATR[7] when TXD signal
is not transmitting. And outputted as complement of
ATR[7] when TXD signal is transmitting.
5
ATR[5]
TXEN Polarity Select:
0b: Asserted output of TXEN is 0b.
1b: Asserted output of TXEN is 1b. (default)
4
ATR[4]
TXEN Control Mode Select:
0b: TXEN is outputted as same as ATR[5], irrespective of TXD
signal. (default)
1b: TXEN is outputted as complement of ATR[5] when TXD
signal is not transmitting, and outputted as same as
ATR[5] when TXD signal is transmitting..
3:2
ATR[3:2]
Not used, always 00b.
1:0
ATR[1:0]
Auto Toggle Enable:
00b: Auto toggle disable (default).
01b: Not used.
10b: Not used.
11b: Auto toggle enable.
Cf. After reset, TXEN and RXEN# ouput ‘0b’.