SB16C1054PCI_Data Sheet_EN

SB16C1054PCI
PCI Target Interface Controller
with Quad-UART
JULY 2013 REV 1.04
51
13.3 Interrupt Enable Register (IER, Page 0)
IER enables each of the seven types of Interrupt, namely receive data ready, transmit
empty, line status, modem status, Xoff received, RTS# state transition from low to high,
and CTS# state transition from low to high. All interrupts are disabled if bit[7:0] are
cleared. Interrupt is enabled by setting appropriate bits. Table 13–3 shows IER bit
settings.
Table 13–3: Interrupt Enable Register Description
Bit
Symbol
Description
7
IER[7]
CTS# Interrupt Enable (Requires EFR[4] = 1):
0b: Disable the CTS# interrupt (default).
1b: Enable the CTS# interrupt.
6
IER[6]
RTS# Interrupt Enable (Requires EFR[4] = 1):
0b: Disable the RTS# interrupt (default).
1b: Enable the RTS# interrupt.
5
IER[5]
Xoff Interrupt Enable (Requires EFR[4] = 1):
0b: Disable the Xoff interrupt (default).
1b: Enable the Xoff interrupt.
4
IER[4]
Sleep Mode Enable (Requires EFR[4] = 1):
0b: Disable sleep mode (default).
1b: Enable sleep mode.
3
IER[3]
Modem Status Interrupt Enable:
0b: Disable the modem status register interrupt (default).
1b: Enable the modem status register interrupt.
2
IER[2]
Receive Line Status Interrupt Enable:
0b: Disable the receive line status interrupt (default).
1b: Enable the receive line status interrupt.
1
IER[1]
Transmit Holding Register Interrupt Enable:
0b: Disable the THR interrupt (default).
1b: Enable the THR interrupt.
0
IER[0]
Receive Buffer Register Interrupt Enable:
0b: Disable the RBR interrupt (default).
1b: Enable the RBR interrupt.