SB16C1054PCI_Data Sheet_EN

SB16C1054PCI
PCI Target Interface Controller
with Quad-UART
JULY 2013 REV 1.04
36
retransmitted because external device has reported that it can accept more data. These
operations prevent overrun during communication and if hardware flow control is
disabled and transmit data rate exceeds RX FIFO service latency, overrun error occurs.
12.2.1 Auto-RTS
To enable Auto-RTS, EFR[6] should be set to 1b. Once enabled, RTS# outputs 0b. If the
number of received data in RX FIFO is larger than the value stored in FUR, RTS# will
be changed to 1b and if not, holds 0b. This state indicates that RX FIFO can accept
more data. After RTS# changed to 1b and reported to the CPU that it cannot accept
more data, the CPU reads the data in RX FIFO and then the amount of data in RX FIFO
reduces. When the amount of data in RX FIFO equals the value written in FLR, RTS#
changes to 0b and reports that it can accept more data. That is, if RTS# is 0b now,
RTS# is not changed to 1b until the amount in RX FIFO exceeds the value set in FUR.
But if RTS# is 1b now, RTS# is not changed to 0b until the amount in RX FIFO equals
the value written in FLR.
The value of FUR and FLR is determined by FIFO mode. If FCR[7:6] holds 00b, ’01’,
‘10’, and 11b, FUR stores 8, 16, 56, and 60, respectively. And if FCR[5:4] holds
00b, ’01’, ‘10’, and 11b, FLR stores 0, 8, 16, and 56, respectively in 64-byte FIFO. In
256-byte FIFO mode, users can write FUR and FLR values as they want and use them.
But the value of FUR must be larger than that of FLR. While Auto-RTS is enabled, you
can verify if RTS# is 0b or 1b by FSR[5]. If FSR[5] is 0b, RTS# is 0b and if 1b, RTS# is
1b, too.
When IER[6] is set to 1b and RTS# is changed from 0b to 1b by Auto-RTS function,
interrupt occurs and it is displayed on ISR[5:0]. Interrupts by Auto-RTS function are
removed if MSR is read. RTS# is changed from 0b to 1b after the first STOP bit is
received. Figure 12–1 shows the RTS# timing chart while Auto-RTS is enabled.
In Figure 12–1, Data Byte n-1 is received and RTS# is deasserted when the amount of
data in RX FIFO is larger than the value written in FUR. UART completes transmitting
new data (DATA BYTE n) which has started being transmitted even though external
UART recognizes RTS# has been deasserted. After that, the device stops transmitting
more data. If CPU reads data of RX FIFO, the value of RCR decreases and then if that
value equals that of FLR, RTS# is asserted for external UART to transmit new data.
FLR + 1 FLR + 0
RCR[7:0]
START
FUR + 1FUR + 0
RTS#
DATA BYTE n STOP
RXD
DATA BYTE n
STARTSTOPDATA BYTE n-1
FUR - 0FUR - 1
START
FUR -0
IOR#
DATA BYTE 2DATA BYTE 1
Figure 12–1: RTS# Functional Timing