SB16C1054PCI_Data Sheet_EN

SB16C1054PCI
PCI Target Interface Controller
with Quad-UART
JULY 2013 REV 1.04
32
11.8 Interrupt Mask Register (IMR)
IMR enables or disables each interrupt of Serial 4 ports.
Table 11–7: Interrupt Mask Register Description
Bit
Symbol
Description
7
IMR[7]
Not used.
6
IMR[6]
Not used.
5
IMR[5]
Not used.
4
IMR[4]
Not used.
3
IMR[3]
0b: Disables Port4 interrupt.
1b: Enables Port4 interrupt.
2
IMR[2]
0b: Disables Port3 interrupt.
1b: Enables Port3 interrupt.
1
IMR[1]
0b: Disables Port2 interrupt.
1b: Enables Port2 interrupt.
0
IMR[0]
0b: Disables Port1 interrupt.
1b: Enables Port1 interrupt.
11.9 Interrupt Poll Register (IPR)
IPR indicates interrupt generation state of Port 1 ~ Port 4.
Table 11–8: Interrupt Poll Register Description
Bit
Symbol
Description
7
IPR[7]
Not used.
6
IPR[6]
Not used.
5
IPR[5]
Not used.
4
IPR[4]
Not used.
3
IPR[3]
0b: Port4 interrupt has occurred.
1b: Port4 interrupt has not occurred.
2
IPR[2]
0b: Port3 interrupt has occurred.
1b: Port3 interrupt has not occurred.
1
IPR[1]
0b: Port2 interrupt has occurred.
1b: Port2 interrupt has not occurred.
0
IPR[0]
0b: Port1 interrupt has occurred.
1b: Port1 interrupt has not occurred.