SB16C1054PCI_Data Sheet_EN

SB16C1054PCI
PCI Target Interface Controller
with Quad-UART
JULY 2013 REV 1.04
24
8.2.4 Power Management Control/Status Register (44~45h)
This 16bit Register manages PCI Function’s Power Management state and it is also
used to enable and monitor PME.
Table 8–8: Power Management Control/Status Register
Bit
Type
Description
15
RW
PME_Status: This bit is set when the function would assert the PME# signal
independent of the state of the PME_En bit.
Writing 1b to this bit will clear it and cause the function to stop asserting a PME# (if
enabled). Writing 0b has no effect.
This bit is sticky and must be explicitly cleared by the OS each time the OS is initially
loaded since this device supports PME# from D3
cold
,
14:13
RO
Data Scale: This device did not implement Data Scale and hardwired to 00b.
12:9
RO
Data Select: This device did not implement Data Select and hardwired to 0000b
8
RW
PME_En: If PME_En is set to 1b, then the function can assert PME#. If PME_En is
cleared to 0b, then the function do not assert PME#. This bit is sticky and must be
explicity cleared by the OS each time the device is initially loaded since this device is
supported to PME# from D3
cold
.
7:4
RO
Reserved: Hardwired to 0b.
3
RO
No_Soft_Reset: Device does not execute internal reset when changing from D3
hot
to
D0 through software control of PowerState bits. It’s because full Re-Initialization is not
needed for device to return to D0. Hardwired to 0b.
2
RO
Reserved: Hardwired to 0b.
1:0
RW
PowerState: PM S/W can decide Power Management state by configuring this section.
PowerState = 00b means D0 state
PowerState = 01b means D1 state
PowerState = 10b means D2 state
PowerState = 11b means D3
hot
state