SB16C1054PCI_Data Sheet_EN

SB16C1054PCI

PCI Target Interface Controller

with Quad-UART

JULY 2013 REV 1.04

8.1.5 Revision

This register shows device revision. Manufacturer can assign it freely and must be

downloaded from serial EEPROM. If you do not prepare Revision ID, you can use B0h

given to SystemBase. It is also related to software device driver installation.

8.1.6 Class Code

This register contains descriptions on functions the device implements and must be

downloaded from serial EEPROM. It is divided as Base Class, Sub Class and

Programming Interface in bytes. It must be set to the values provided by PCI Bus

Specification.

If you do not prepare Class Code, you can use 070002h given to SystemBase.

This Class Code(070002h) means a serial communication card adaptor.

Base Class Code is 07h(communication controller), Sub Class Code is 00h(serial

controller) and Programming Interface is 02h(16C550 compatible).

8.1.7 Cache Line Size

This register assigns size of system’s Cache Line. It is implemented as [RW] for

compatibility with existing PCI. It is not supported and hardwired to 0000_0000b.

8.1.8 Latency Timer

This register assigns latency clock related to bus master which does burst access. It is

not supported and hardwired to 0000_0000b.

8.1.9 Header Type

Configuration Space Header type and [ RO]

Bit[7] : Shows whether device is Multi Function or Single Function. This product has

default value 0b since it only supports Single Function.

Bit[6:0] : Assign header type after 10h. 00h is target device, 01h is PCI-to-PCI Bridge

and 02h is CardBus bridge. This product has default value 00 since it is a target device.

8.1.10 BIST(Built-In Self Test)

Table 8–4: BIST

Bit

Type

Description

BIST Capable: Hardwired to 0b.

Start BIST: Hardwired to 0b.

5:4

Reserved: Hardwired to 00b.

3:0

Completion Code: Hardwired to 0000b.