SB16C1054PCI_Data Sheet_EN

SB16C1054PCI
PCI Target Interface Controller
with Quad-UART
JULY 2013 REV 1.04
2
CONTENTS
1. Description ................................................................................................................................................. 5
2. Features ..................................................................................................................................................... 5
2.1 PCI Interface .................................................................................................................................... 5
2.2 Internal Quad-UART ......................................................................................................................... 5
2.3 Development Kit ............................................................................................................................... 6
3. Ordering Information .................................................................................................................................. 6
4. Block Diagram ........................................................................................................................................... 7
5. Applications ................................................................................................................................................ 8
5.1 Serial 4-port ...................................................................................................................................... 8
6. Pin Configuration ....................................................................................................................................... 9
6.1 Pin Configuration for 144-Pin LQFP Package .................................................................................. 9
7. Configuration Loader ............................................................................................................................... 16
7.1 Serial EEPROM Information Table ................................................................................................. 16
8. PCI Configuration Space ......................................................................................................................... 18
8.1 Configuration Space Map of SB16C1054PCI ................................................................................ 18
8.1.1 Vendor ID ............................................................................................................................. 19
8.1.2 Device ID .............................................................................................................................. 19
8.1.3 Command Register .............................................................................................................. 19
8.1.4 Status Register ..................................................................................................................... 20
8.1.5 Revision ............................................................................................................................... 21
8.1.6 Class Code ........................................................................................................................... 21
8.1.7 Cache Line Size ................................................................................................................... 21
8.1.8 Latency Timer ....................................................................................................................... 21
8.1.9 Header Type ......................................................................................................................... 21
8.1.10 BIST(Built-In Self Test) ....................................................................................................... 21
8.1.11 Base Address Registers ..................................................................................................... 22
8.2 Power Management Registers of SB16C1054PCI ........................................................................ 23
8.2.1 Capability ID (40h) ............................................................................................................... 23
8.2.2 Pointer to Next Capability (41h) ........................................................................................... 23
8.2.3 Power Management Capabilities (42~43h) .......................................................................... 23
8.2.4 Power Management Control/Status Register (44~45h) ....................................................... 24