SB16C1054PCI_Data Sheet_EN

SB16C1054PCI
PCI Target Interface Controller
with Quad-UART
JULY 2013 REV 1.04
18
8. PCI Configuration Space
PCI Configuration offers one type of Configuration Space access method.
- PCI Compatible Configuration method
PCI Compatible Configuration method is compatible with PCI version 2.3 and higher
and supports 100% binary compatibility to software for operating system agreed bus list
and organization.
From 0 byte up to 256 bytes is called PCI Compatible Configuration Space
8.1 Configuration Space Map of SB16C1054PCI
Table 8–1: Configuration Space Map
Bit[31:24]
Bit[23:16]
Bit[15:8]
Bit[7:0]
Reg00
Device ID
Vendor ID
Reg04
Status Register
Command Register
Reg08
Class Code
Revision
Reg0C
BIST
Header Type
Latency Timer
Cache Line Size
Reg10
BAR0 (UART)
Reg14
BAR1 (OPTION REGISTER)
Reg18
BAR2 (Reserved)
Reg1C
BAR3 (Reserved)
Reg20
BAR4 (Reserved)
Reg24
BAR5 (Reserved)
Reg28
CardBus CIS Pointer
Reg2C
Subsystem ID
Subsystem Vendor ID
Reg30
Expansion ROM BAR
Reg34
Reserved
Cap. Pointer
Reg38
Reserved
Reg3C
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
Reg40
Power Management Capability
Reg44
Power Management Control & Status
Reg48~FF
Reserved
Configuration Space of SB16C1054PCI can be divided into 2 following functions.
- PCI Compatible Configuration Registers
- Power Management Registers
PCI Compatible Configuration Registers are from Reg00 to Reg3C and these parts are
compatible with existing PCI Configuration Registers. Power Management Registers are
from Reg40 to Reg44.
SB16C1054PCI uses Configuration Register of Header Type0 which is used as
Endpoint.
Following is a detailed description of PCI Compatible Configuration Register.