SB16C1054_Data Sheet_EN

SB16C1054
QUAD UART WITH 256-BYTE FIFO
FEBRUARY 2009 REV 1.0
5
23
7. Register Descriptions
Each UART channel in the SB16C1054 has its own set of registers selected by address
lines A2, A1, and A0 with a specific channel selected. The complete register set is shown
on Table 7 and Table 8.
Table 7: Internal Registers Map
Address
A[2:0]
Page 0 Page 1 Page 2 Page 3 Page 4
LCR[7] = 0
MCR[6] = 0
LCR[7] = 1
LCR[7:0] ≠
≠≠
≠ BFh
LCR[7] = 0
MCR[6] = 1
LCR = BFh
PSR[0] = 0
LCR = BFh
PSR[0] = 1
0h THR/RBR DLL — PSR PSR
1h IER DLM GICR ATR AFR
2h FCR/ISR GISR EFR XRCR
3h LCR
4h MCR XON1 TTR
5h LSR TCR XON2 RTR
6h MSR RCR XOFF1 FUR
7h SPR FSR XOFF2 FLR