DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
95
Table 14–1: Pin Description of MIO Bus
TM
Signal Name
Pin No.
I/O
Signal Description
MD[0]
86
I/O
8-bit Data Bus of MIO Bus
TM
It used for exchange 8-bit data between UART
and SB16C1053APCI.
MD[1]
83
I/O
MD[2]
82
I/O
MD[3]
81
I/O
MD[4]
80
I/O
MD[5]
79
I/O
MD[6]
78
I/O
MD[7]
77
I/O
MA[0]
63
O
3-bit Address Bus of MIO Bus
TM
It used for selecting address of UART registers.
MA[1]
62
O
MA[2]
59
O
MCS[0]#
58
O
Chip Selection of MIO Bus
TM
for 1
st
external
UART
MCS[1]#
70
O
Chip Selection of MIO Bus
TM
for 2
nd
external
UART
MCS[2]#
55
O
Chip Selection of MIO Bus
TM
for 3
rd
external
UART
MCS[3]#
54
O
Chip Selection of MIO Bus
TM
for 4
th
external
UART
MIRQ[0]
74
I
Interrupt Request of MIO Bus
TM
from 1
st
external
UART
MIRQ[1]
75
I
Interrupt Request of MIO Bus
TM
from 2
nd
external
UART
MIRQ[2]
76
I
Interrupt Request of MIO Bus
TM
from 3
rd
external
UART
MIRQ[3]
71
I
Interrupt Request of MIO Bus
TM
from 4
th
external
UART
MIOR#
64
O
Read Strobe of MIO Bus
TM
MIOW#
65
O
Write Strobe of MIO Bus
TM
MRESET
68
O
Reset of MIO Bus
TM