DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
89
13.6.1 Pin Descriptions in the ECP Mode
Table 13–11: Pin Description in ECP Mode
Signal
Name
Type
ECP Protocol Signal Description
nSTROBE
O
Host Clock (HostClk): SB16C1053APCI assert HostClk to instruct
the peripheral to latch the data on PD[7:0] in forward direction. The
peripheral latch data on the rising edge of HostClk. HostClk
handshake with PeriphAck. After the peripheral latch the data on
PD[7:0], it de-assert PeripheAck. After SB16C1053APCI detects
PeriphAck asserted, it de-asserts HostClk. In reverse direction,
HostClk is not used.
BUSY
I
Peripheral Acknowledge (PeriphAck): The peripheral asserts this
signal to acknowledge for the receipt of data in forward direction.
After the peripheral detects HostClk going high for termination of
transfer, it de-asserts this signal. PeriphAck handshake with
HostClk. In reverse direction, PeriphAck is low. The peripheral
assert this signal to indentify Run Length Encoded (RLE) data.
nACK
I
Peripheral Clock (PeriphClk): The peripheral asserts this signal to
indicated data on the data bus is valid in reverse direction. After
the peripheral detects HostAck going high, it de-asserts this signal.
PeriphClk handshake with HostAck.
SELECT
I
XFLAG (X flag): The peripheral asserts this signal to indicate that
peripheral is on-line. This signal is indicated via STAT register.
PERROR
I
Acknowledge Reverse (nAckReverse): The peripheral asserts this
signal to acknowledge for reverse transfer request from host.
nAckReverse handshake with nReverseRequest. This signal is
indicated via STAT register.
nFAULT
I
Peripheral Request (nPeriphReqest): The peripheral asserts this
signal to request a reverse transfer. This signal is indicated via
STAT register.
nINIT
O
Reverse Request (nReverseRequest): The host asserts this signal
to request reverse transfer direction. The host de-asserts this
signal for forward transfer direction. This signal is controlled via
CTRL register.
nAUTOFD
O
Host Acknowledge (HostAck): SB16C1053APCI asserts this signal
to request data in reverse direction. HostAck handshake with
PeriphClk. SB16C1053APCI de-asserts this signal when
peripheral indicates valid state of the data bus.
HostAck represents whether PD[7:0] contain address, REL or data
in forward direction.
PD[7:0]
I/O
DATA: 8 bits bi-directional data bus for data, address, RLE data.
nSLCTIN
O
ECP Mode (ECPmode): The host de-asserts this signal during
ECP operation.