DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
88
13.5.2 Register Descriptions in the EPP Mode
Table 13–10: Register Description in EPP Mode
Address
BAR2 +
Abbreviation
Register Name
Access
0h
DATA
Data Register
R/W
1h
STAT
Status Register
R
2h
CTRL
Control Register
R/W
3h
ADDSTR
Address Strobe Register
R/W
4h ~ 7h
DATASTR
Data Strobe Register
R/W
The description of DATA register is same with Data Register of 13.2.1 Register Descriptions in
the Compatibility Mode.
The description of STAT register is same with Status Register of 13.2.1 Register Descriptions in
the Compatibility Mode.
The description of CTRL register is same with Control Register of 13.2.1 Register Descriptions in
the Compatibility Mode.
The ADDSTR register provides a peripheral address to the peripheral via PD[7:0] during a host
write, and to the host via PD[7:0] during a host address read operation. An automatic address
strobe is generated on the parallel port interface when data is read or written to this register.
The DATASTR registers provide data from the host to the peripheral via PD[7:0] during a write
operation, and data from the peripheral to the host during a read operation. An automatic data
strobe is generated on the parallel port interface when data is read or written to these registers.
13.5.2 EPP Mode Operation
If no EPP Read, Write or Address cycle is currently being executed, the Peripheral data bus may
be used in either Compatibility Mode (and/or Nibble Mode) or PS/2 (Byte) Mode. In this
condition, all output signals (NSTROBE, NAUTOFD and NINIT) are set by the CTRL register and
direction is controlled by the PDIR bit of the CTRL register.
Before an EPP cycle is executed, the control register PDIR bit must be set to 0 (by writing 04h or
05h to the CTRL register). If PDIR is left set to 1, the SB16C1053APCI will not be able to
perform a write and will appear instead to perform an EPP read on the parallel bus without any
error being indicated.
If an EPP bus cycle does not terminate within 10ms, the EPP timeout flag will be set and all
following EPP bus cycles will be aborted until this flag is cleared. The flag is cleared by writing to
the STAT register.
13.6 ECP Mode
EXTENDED CAPABILITIES PORT (ECP) MODE provides an asynchronous, byte wide, bi-
directional channel. An interlocked handshake replaces the Compatibility Mode's minimum timing
requirements. A control line is provided to distinguish between command and data transfers.