DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
87
13.5 EPP Mode
ENHANCED PARALLEL PORT (EPP) MODE provides an asynchronous, byte wide, bi-irectional
channel controlled by the host device. This mode provides separate address and data cycles
over the eight data lines of the interface.
The Enhanced Parallel Port (EPP) was designed in a joint venture between Intel, Xircom &
Zenith Data Systems. EPP Ports were first specified in the EPP 1.7 standard, and then later
included in the IEEE 1284 standard released in 1994. EPP has two standards, EPP 1.7 and EPP
1.9. EPP has a typical transfer rate in the order of 500KB/s to 2MB/s.
13.5.1 Pin Descriptions in the EPP Mode
Table 13–9: Pin Description in EPP Mode
Signal
Name
Type
EPP Protocol Signal Description
STROBE#
O
WRITE (write#): It indicates an address or data read/write to the
peripheral. When the value is low, it works as write operation.
When the value is high, it works as read operation.
BUSY
I
WAIT (wait#): The peripheral assert low to indicate that the
peripheral device is not ready. When BUSY is low,
SB16C1053APCI make internal signal, IOCHRDY to low for the
longer I/O cycle. The peripheral deassert high to indicate that the
transfer of data or address is completed.
ACK#
I
Interrupt Request (Intr): The peripheral asserts to generate
interrupt to the host. When this signal is low and interrupt enabled,
interrupt is generated to the host.
SELECT
I
SELECT: The peripheral asserts to indicate that the device is on
line. This signal is indicated via STAT register.
PERROR
I
Paper Error: The peripheral asserts to indicate that there is an
error in the paper path. This signal is indicated via the STAT
register.
FAULT#
I
FAULT: The peripheral asserts to indicate that an error has
occurred. This signal is indicated via the STAT register.
INIT#
O
INITIALIZE: The host asserts to reset the peripheral device. This
signal is controlled via CTRL register.
AUTOFD#
O
Data Strobe (DStrb#): The host asserts to indicate that valid data is
present on data bus(PD[7:0]). The peripheral use DStrb# as data
latch point.
PD[7:0]
I/O
DATA: The 8-bit bi-directional bus provides address or data.
When write cycle is working, this data bus work as output.
When read cycle is working, this data
SLCTIN#
O
Address Strobe (AStrb#): The host asserts to indicate that a valid
address is present on PD[7:0]. The peripheral use AStrb# as
address latch point.