DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
78
Table 12–14: Auto Toggle Control Register Description
Bit
Symbol
Description
7
ATR[7]
RXEN# Polarity Select:
0b: Asserted output of RXEN# is 0b.
1b: Asserted output of RXEN# is 1b. (default)
6
ATR[6]
RXEN# Enable
0b: RXEN# is outputted as same as ATR[7], irrespective of
TXD signal. (default)
1b: RXEN# is outputted as same as ATR[7] when TXD signal
is not transmitting. And outputted as complement of
ATR[7] when TXD signal is transmitting.
5
ATR[5]
TXEN Polarity Select:
0b: Asserted output of TXEN is 0b.
1b: Asserted output of TXEN is 1b. (default)
4
ATR[4]
TXEN Enable:
0b: TXEN is outputted as same as ATR[5], irrespective of TXD
signal. (default)
1b: TXEN is outputted as complement of ATR[5] when TXD
signal is not transmitting, and outputted as same as
ATR[5] when TXD signal is transmitting..
3:2
ATR[3:2]
Auto Toggle De-assertion Mode:
You can select the delta between TXEN/RXEN# de-assertion
and stop bit of frame.
00b: 0ns(∆2) 01b: 75ns(∆2) 10b: 150ns(∆2) 11b: 300ns(∆2)
1:0
ATR[1:0]
Auto Toggle Assertion Mode:
You can select the delta between TXEN/RXEN# assertion and
start bit of frame.
When ATR[3:2]≠11b,
00b: 0ns(∆1), 01b: 75ns(∆1), 10b: 150ns(∆1), 11b: 300ns(∆1)
When ATR[3:2] = 11b,
00b: 0.6us(∆1), 01b: 1us(∆1), 10b: 1.5us(∆1), 11b: 3us(∆1)
Cf. After reset, TXEN and RXEN# output ‘0b’.
Figure 12–1: Control of Assertion & Deassertion time in Auto Toggle mode