DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
76
12.17 Flow Control Status Register (FSR, Page 2)
FSR show the status of operation of TX Hardware Flow Control, RX Hardware Flow
Control, TX Software Flow Control, and RX Software Flow Control.
Table 1212: Flow Control Status Register Description
Bit
Symbol
Description
7:6
FSR[7:6]
Not used, always 00b.
5
FSR[5]
TX Hardware Flow Control Status:
0b: When FIFO or Auto-RTS flow control is disabled.
If FIFO and Auto-RTS flow control is enabled, it means the
number of data received in RX FIFO at the first time is less
than the value of FUR, or it means the number of data in RX
FIFO was more than the value of FUR and after the CPU
read them, the number of data that remains unread is less
than or equal to the value of FLR. That is, UART reports
external device that it can receive more characters.
1b: It shows that the number of data received in RX FIFO
exceeds the value of FUR and UART reports external
device that it cannot receive more data. If RX FIFO has
space to store more data, new data are stored in RX FIFO
but after it gets full, they are lost.
For more details, refer to 12.2 Hardware Flow Control.
4
FSR[4]
TX Software Flow Control Status:
0b: When FIFO or Software flow control is disabled.
If FIFO and Software flow control is enabled, it means
the number of data received in RX FIFO at the first time is
less than the value of FUR, or it means the number of data
in RX FIFO was more than the value of FUR and after the
CPU read them, the number of data that remains unread
after the CPU read the data received in RX FIFO is less
than or equal to the value of FLR. That is, UART transmits
Xon character to report external device that it can receive
more data.
1b: It shows that the number of data received in RX FIFO
exceeds the value of FUR and transmitting Xoff character to
report external device that it cannot receive more data. If
RX FIFO has space to store more data, new data are stored
in RX FIFO but after it gets full, they are lost.
For more details, refer to 12.3 Software Flow Control.
3:2
FSR[3:2]
Not used, always 00b.
1
FSR[1]
RX Hardware Flow Control Status: