DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
73
12.9 Auto Toggle Control Register (ACR, Page 0 & Page 1)
Address 5h is used for LSR (Line Status Register) in the existent UART Core with R/W
permission. But we change to use address 5h with write permission to ACR (Auto
Toggle Control Register).
Originally we use ATR (Auto Toggle Register) in page 3 for the setting of auto toggling.
To decrease inconvenience of accessing ATR, we make other access route for the
setting of Auto Toggling. That is ACR in page 0. So you can see the same functions
between ATR and ACR.
Table 12–9: Auto Toggle Control Register Description
Bit
Symbol
Description
7
ACR[7]
RXEN# Polarity Select: It is used for controlling RXEN# output.
0b: Asserted output of RXEN# is 0b.
1b: Asserted output of RXEN# is 1b. (default)
It support the function same as bit7 of ATR.
6
ACR[6]
Reserved.
5
ACR[5]
TXEN Polarity Select: It is used for controlling TXEN output.
0b: Asserted output of RXEN# is 0b.
1b: Asserted output of RXEN# is 1b. (default)
It support the function same as bit5 of ATR.
4:0
ACR[4:0]
Reserved.
12.10 Modem Status Register (MSR, Page 0)
MSR provides the current status of control signals from modem or auxiliary devices.
MSR[3:0] are set to 1b when input from modem changes and cleared to 0b as soon as
CPU reads MSR. Table 12–10 shows MSR bit settings.
Table 12–10: Modem Status Register Description
Bit
Symbol
Description
7:4
MSR[7]
DCD Input Status:
Complement of Data Carrier Detect (DCD#) input.
In loop back mode this bit is equivalent to OUT2 in the MCR.
6
MSR[6]
RI Input Status:
Complement of Ring Indicator (RI#) input.
In loop back mode this bit is equivalent to OUT1 in the MCR.
5
MSR[5]
DSR Input Status:
Complement of Data Set Ready (DSR#) input.
In loop back mode this bit is equivalent to DTR in the MCR.
4
MSR[4]
CTS Input Status:
Complement of Clear To Send (CTS#) input.
In loop back mode this bit is equivalent to RTS in the MCR.