DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
70
This bit will return to 0b after resetting FIFO.
1
FCR[1]
RX FIFO Reset:
0b: No RX FIFO reset (default)
1b: Reset RX FIFO pointers and RX FIFO level counter logic.
This bit will return to 0b after resetting FIFO.
0
FCR[0]
FIFO enable:
0b: Disable the TX and RX FIFO (default).
1b: Enable the TX and RX FIFO
12.6 Line Control Register (LCR, Page 0)
LCR controls the asynchronous data communication format. The word length, the number
of stop bits, and the parity type are selected by writing the appropriate bits to the LCR.
Table 12–6 shows LCR bit settings.
Table 12–6: Line Control Register Description
Bit
Symbol
Description
7
LCR[7]
Divisor Latch Enable:
0b: Disable the divisor latch (default).
1b: Enable the divisor latch.
6
LCR[6]
Break Enable:
0b: No TX break condition output (default).
1b: Forces TXD output to 0b, for alerting the communication
terminal to a line break condition.
5
LCR[5]
Set Stick Parity:
LCR[5:3] = xx0b: No parity is selected.
LCR[5:3] = 0x1b: Stick parity disabled. (default)
LCR[5:3] = 101b: Stick parity is forced to 1b.
LCR[5:3] = 111b: Stick parity is forced to 0b.
4
LCR[4]
Parity Type Select:
LCR[5:3] =001b: Odd parity is selected.
LCR[5:3] =011b: Even parity is selected.
3
LCR[3]
Parity Enabled:
0b: No parity (default).
1b: A parity bit is generated during the transmission and
the receiver checks for receive parity.
2
LCR[2]
Number of Stop Bits:
LCR[2:0] = 0xxb: 1 stop bit (word length = 5, 6, 7, 8).
LCR[2:0] = 100b: 1.5 stop bits (word length = 5).
LCR[2:0] = 11xb or 1x1b: 2 stop bits (word length = 6, 7. 8).
1:0
LCR[1:0]
Word Length Bits:
00b: 5 bits (default). 01b: 6 bits.
10b: 7 bits. 11b: 8 bits.