DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
69
Table 12–4: Interrupt Status Register Description…continued
Bit
Interrupt Priority List and Reset Functions
5:0
Priority
Interrupt Type
Interrupt Source
Interrupt Reset Control
00_0001
―
None
None
―
00_0110
1
Receiver Line Status
OE, PE, FE, BI
Address Incoming Event (9
th
bit is ‘1’)
Readi g the LSR.
00_0100
2
Receive Data Available
Receiver data available, reaches
trigger level.
Reading the RBR or RCR
falls below trigger level.
00_ 100
2
Character Timeout Indi-
cation
At least one data is in RX FIFO and
there are no more data in FIFO during
four character time.
Reading the RBR.
00_0010
3
Transmit Holding
Register Empty
When THR is empty or TCR passes
above trigger level (FIFO enable).
Reading the ISR or write
data on THR.
00_0000
4
Modem Status
CTS#, DSR#, DCD#, RI#
Reading the MSR.
01_0000
5
Receive Xoff or Special
Character
Detection of a Xoff or special character.
Detection of Special Character
Reading the ISR.
10_0000
6
RTS#, CTS# Status
during Auto RTS/CTS
flow control
RTS# pin or CTS# pin change state from
0b to 1b.
Reading the ISR.
12.5 FIFO Control Register (FCR, Page 0)
FCR is used for enabling the FIFOs, clearing the FIFOs, setting transmit/receive FIFO
trigger level, and selecting the DMA modes. Table 12–5 shows FCR bit settings.
Table 12–5: FIFO Control Register Description
Bit
Symbol
Description
7:6
FCR[7:6]
RX FIFO Trigger Level Select:
00b: 8 characters (default)
01b: 16 characters
10b: 56 characters
11b: 60 characters
5:4
FCR[5:4]
TX FIFO Trigger Level Select:
00b: 8 characters (default)
01b: 16 characters
10b: 32 characters
11b: 56 characters
FCR[5:4] can only be modified and enabled when EFR[4] is set.
3
FCR[3]
DMA Mode Select:
0b: Set DMA mode 0 (default)
1b: Set DMA mode 1
2
FCR[2]
TX FIFO Reset:
0b: No TX FIFO reset (default)
1b: Reset TX FIFO pointers and TX FIFO level counter logic.