DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
68
4
IER[4]
Sleep Mode Enable (Requires EFR[4] = 1):
0b: Disable sleep mode (default).
1b: Enable sleep mode.
3
IER[3]
Modem Status Interrupt Enable:
0b: Disable the modem status register interrupt (default).
1b: Enable the modem status register interrupt.
2
IER[2]
Receive Line Status Interrupt Enable:
0b: Disable the receive line status interrupt (default).
1b: Enable the receive line status interrupt.
1
IER[1]
Transmit Holding Register Interrupt Enable:
0b: Disable the THR interrupt (default).
1b: Enable the THR interrupt.
0
IER[0]
Receive Buffer Register Interrupt Enable:
0b: Disable the RBR interrupt (default).
1b: Enable the RBR interrupt.
12.4 Interrupt Status Register (ISR, Page 0)
The UART provides multiple levels of prioritized interrupts to minimize software work
load. ISR provides the source of interrupt in a prioritized manner.
Table 12–4 shows ISR[7:0] bit settings.
Table 12–4: Interrupt Status Register Description
Bit
Symbol
Description
7
ISR[7]
FCR[0]/256 TX FIFO Empty:
When 256-byte FIFO mode is disabled (default).
Mirror the content of FCR[0].
When 256-byte FIFO mode is enabled.
0b: 256-byte TX FIFO is full.
1b: 256-byte TX FIFO is not full.
When TCR is ‘00h’, there are two situations of TX FIFO full and TX FIFO empty. If 256 TX
empty bit is 1b, it means TX FIFO is empty and if 0b, it means 256 bytes character is fully
stored in TX FIFO.
6
ISR[6]
FCR[0]/256 RX FIFO Full:
When 256-byte FIFO mode is disabled (default).
Mirror the content of FCR[0].
When 256-byte FIFO mode is enabled.
0b: 256-byte RX FIFO is not full.
1b: 256-byte RX FIFO is full.
When RCR is 00h, there are two situations of RX FIFO full and RX FIFO empty. If 256 RX
empty bit is 1b, it means 256 bytes character is fully stored in RX FIFO and if 0b, it means
RX FIFO is empty.