DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
67
5h
RTR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
6h
FUR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7h
FLR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
12.1 Transmit Holding Register (THR, Page 0)
The transmitter section consists of the Transmit Holding Register (THR) and Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO or a 256-byte FIFO. The THR
receives data and shifts it into the TSR, where it is converted to serial data and moved
out on the TX terminal. If the FIFO is disabled, location zero of the FIFO is used to store
the byte. Characters are lost if overflow occurs.
In the 9-bit transmission mode, this register works as TDR (Transmit 9-bit Data
Register). Please refer description of TAR, 12.13 Transmit 9-bit Address Register
12.2 Receive Buffer Register (RBR, Page 0)
The receiver section consists of the Receive Buffer Register (RBR) and Receive Shift
Register (RSR). The RBR is actually a 64-byte FIFO or a 256-byte FIFO. The RSR
receives serial data from external terminal. The serial data is converted to parallel data
and is transferred to the RBR. This receiver section is controlled by the line control
register. If the FIFO is disabled, location zero of the FIFO is used to store the
characters. If overflow occurs, characters are lost. The RBR also stores the error status
bits associated with each character.
12.3 Interrupt Enable Register (IER, Page 0)
IER enables each of the seven types of Interrupt, namely receive data ready, transmit
empty, line status, modem status, Xoff received, RTS# state transition from low to high,
and CTS# state transition from low to high. All interrupts are disabled if bit[7:0] are
cleared. Interrupt is enabled by setting appropriate bits. Table 12–3 shows IER bit
settings.
Table 12–3: Interrupt Enable Register Description
Bit
Symbol
Description
7
IER[7]
CTS# Interrupt Enable (Requires EFR[4] = 1):
0b: Disable the CTS# interrupt (default).
1b: Enable the CTS# interrupt.
6
IER[6]
RTS# Interrupt Enable (Requires EFR[4] = 1):
0b: Disable the RTS# interrupt (default).
1b: Enable the RTS# interrupt.
5
IER[5]
Xoff Interrupt Enable (Requires EFR[4] = 1):
0b: Disable the Xoff interrupt (default).
1b: Enable the Xoff interrupt.