DataSheet_SB16C1053APCI_v106
SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
65
4h
XON1b: Xon1 Character Register
Read/Write
LCR = BFh, PSR[0] = 0
5h
XON2 : Xon2 Character Register
Read/Write
LCR = BFh, PSR[0] = 0
6h
XOFF1b: Xoff1 Character Register
Read/Write
LCR = BFh, PSR[0] = 0
7h
XOFF2 : Xoff2 Character Register
Read/Write
LCR = BFh, PSR[0] = 0
SCR : Special Character Register
Page 4 Registers
0h
PSR : Page Select Register
Read/Write
LCR = BFh, PSR[0] = 0,
LCR = BFh, PSR[0] = 1
1h
AFR : Additional Feature Register
Read/Write
LCR = BFh, PSR[0] = 1
2h
XRCR : Xoff Re-transmit Count Register
Read/Write
LCR = BFh, PSR[0] = 1
3h
LCR : Line Control Register
Read/Write
—
4h
TTR : Transmit FIFO Trigger Level Register
Read/Write
LCR = BFh, PSR[0] = 1
5h
RTR : Receive FIFO Trigger Level Register
Read/Write
LCR = BFh, PSR[0] = 1
6h
FUR : Flow Control Upper Threshold Register
Read/Write
LCR = BFh, PSR[0] = 1
7h
FLR : Flow Control Lower Threshold Register
Read/Write
LCR = BFh, PSR[0] = 1
Table 12–2: Internal Registers Description
Addr.
A[2:0]
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page 0 Registers
0h
THR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TDR
Transmit 9-bit Data Register with logic “0” of 9
th
bit (Accessible when MDE is set to ‘1’)
0h
RBR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1h
IER
0/CTS#
Interrupt
Enable
0/RTS#
Interrupt
Enable
0/Xoff
Interrupt
Enable
0/Sleep
Mode
Enable
Modem
Status
Interrupt
Enable
Receive
Line Status
Interrupt
Enable
THR
Empty
Interrupt
Enable
Receive
Data
Available
Interrupt
Enable
2h
ISR
FCR[0]/
256-TX
FIFO Empty
FCR[0]/
256-RX
FIFO Full
Interrupt
Priority
Bit 5
Interrupt
Priority
Bit 4
Interrupt
Priority
Bit 3
Interrupt
Priority
Bit 2
Interrupt
Priority
Bit 1
Interrupt
Priority
Bit 0
2h
FCR
RX
Trigger
Level
(MSB)
RX
Trigger
Level
(LSB)
0/TX
Trigger
Level
(MSB)
0/TX
Trigger
Level
(LSB))
DMA
Mode
Select
TX FIFO
Reset
RX
FIFO
Reset
FIFO
Enable
3h
LCR
Divisor
Enable
Set
TX Brake
Set
Parity
Parity
Type
Select
Parity
Enable
Stop
Bits
Word
Length
Bit 1
Word
Length
Bit 0
4h
MCR
Clock
Select
Page 2 Select
Xoff Re-Transmit
Access Enable
0/Xon
Any
0/Loop
Back
OUT2/
INTx
Enable
OUT1/ Xoff Re-
Transmit
Enable
RTS#
DTR#
5h
LSR
RX FIFO
Data
THR &
TSR
THR
Empty
Receive
Break
Framing
Error
Parity
Error
Overrun
Error
Receive
Data