DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
63
12. UART Register Descriptions
Each UART channel in the SB16C1050A has its own set of registers selected by address
lines A2, A1, and A0 with a specific channel selected. The complete register set is shown
on Table 12–1 and Table 12–2.
Table 12–1: Internal Registers Map
Address
A[2:0]
Page 0
Page 1
Page 2
Page 3
Page 4
LCR[7] = 0
MCR[6] = 0
LCR[7] = 1
LCR[7:0] ≠ BFh
LCR[7] = 0
MCR[6] = 1
LCR = BFh
PSR[0] = 0
LCR = BFh
PSR[0] = 1
0h
THR(TDR) / RBR
DLL
—
PSR
PSR
1h
IER
DLM
—
ATR
AFR
2h
FCR / ISR
—
EFR
XRCR
3h
LCR
4h
MCR
XON1
TTR
5h
LSR / ACR
TCR
XON2
RTR
6h
MSR / MDR
RCR
XOFF1
FUR
7h
SPR / TAR
FSR
XOFF2
FLR
Table 12–1: Internal Registers Map…continued
Address
A[2:0]
Register
Read/Write
Comments
Page 0 Registers
0h
THR : Transmit Holding Register
TDR : Transmit 9-bit Data Register
RBR : Receive Buffer Register
Write-only
(multi-drop mode)
Read-only
LCR[7] = 0, MCR[6] = 0
1h
IER : Interrupt Enable Register
Read/Write
LCR[7] = 0, MCR[6] = 0
2h
FCR : FIFO Control Register
ISR : Interrupt Status Register
Write-only
Read-only
LCR[7] = 0, MCR[6] = 0,
LCR[7] = 1, LCR ≠ BFh
3h
LCR : Line Control Register
Read/Write
—
4h
MCR : Modem Control Register
Read/Write
LCR[7] = 0, MCR[6] = 0,
LCR[7] = 1, LCR ≠ BFh,
LCR[7] = 0, MCR[6] = 1
5h
LSR : Line Status Register
ACR : Auto Toggle Control Register
Read-only
Write-only
LCR[7] = 0, MCR[6] = 0,
LCR[7] = 1, LCR ≠ BFh
6h
MSR : Modem Status Register
MDR : Multi Drop mode Register
Read-only
Write-only
LCR[7] = 0, MCR[6] = 0,
LCR[7] = 1, LCR ≠ BFh
7h
SPR : Scratch Pad Register
Read/Write
LCR[7] = 0, MCR[6] = 0,