DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
62
If 9
th
bit is checked for ‘1’ through 9-bit communication, it is regarded as address, it can be
differentiated whether packet for right slave if it is compared to slave device. Generally,
this comparison is worked in software level, but SB16C1050A UART Core provides this
comparison function to operate in hardware level. If 9
th
bit is ‘1’, its address has only to be
stored in advance in SCR(Special Character Register), it can be compared to address in
hardware. Of course, if the address designated itself is transmitted in SCR, the software
can be signaled by emerging interrupt. SCR is used for Xon/Xoff that is software flow
control originally and is used for space to store Xoff/Xon character, in case of Multi-Drop
mode, it is used for space to store its address. With this, software and driver’s overhead is
reduced and the performance is improved through automatic comparison in hardware.
11.7.3 Changed Register Map
Table 11–6: UART Register Map
Addr
[2:0]
Page 0
Page 1
Page 2
Page 3
Page 4
LCR[7] = 0
MCR[6] = 0
LCR[7] = 1
LCR[7:0] ≠ BFh
LCR[7] = 0
MCR[6] = 1
LCR = BFh
PSR[0] = 0
LCR = BFh
PSR[0] = 1
0h
THR( TDR )/RB
DLL
—
PSR
PSR
1h
IER
DLM
GICR
ATR
AFR
2h
FCR / ISR
GISR
EFR
XRCR
3h
LCR
4h
MCR
XON1
TTR
5h
ACR / LSR
TCR
XON2
RTR
6h
MDR / MSR
RCR
XOFF1
FUR
7h
SPR / TAR
FSR
XOFF2
FLR
The registers with Bold Character in the upper table are new register or changed register
for 9-bit data transmission. For getting detail description. You can see the detail
description about the register with bold in the Chapter 13. UART Register Descriptions.
Follows are new or changed registers:
- TDR (Transmit 9-bit Data Register) / TAR (Transmit 9-bit Address Register)
- ISR (Interrupt Status Register)
- ACR (Auto Toggle Control Register)
- MDR (Multi Drop mode Register)
- ATR (Auto Toggling Register)
- EFR (Enhanced Feature Register)