DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
56
Figure 11–3: Crystal Clock Circuit Reference Diagram
Table 11–5: Component Values
Frequency Range (MHz)
C1 (pF)
C2 (pF)
R1 (Ω)
R2(Ω)
1.8~8
22
68
220K
470 ~ 1.5K
8~16
33~68
33 ~ 68
220K ~ 2.2M
470 ~ 1.5K
11.6 Break and Time-out Conditions
Break Condition:
Break Condition occurs when TXD signal outputs 0b and sustains for more than one
character.
It occurs if LCR[6] is set to 1b and deleted if 0b. If break condition occurs when normal
data are transmitted on TXD, break signal is transmitted and internal serial data are also
transmitted, but they are not outputted to external TXD pin. When Break condition is
deleted, then they are transmitted to TXD pin.
Figure 11–4 below shows the Break Condition Block Diagram.
Time-out Condition:
When serial data is received from external UART, characters are stored in RX FIFO.
When the number of characters in RX FIFO reaches the trigger level, interrupt is
generated for the CPU to treat characters in RX FIFO. But when the number of
characters in RX FIFO does not reach the trigger level and no more data arrives from
external device, interrupt is not generated and therefore CPU cannot recognize it.
SB16C1050A offers time-out function for this situation. Time-out function generates an
interrupt and reports to CPU when the number of RX FIFO is less than trigger level and
no more data receives for four character time.
Time-out interrupt is enabled when IER[2] is set to 1b and can be verified by ISR.
CRYSTALR1
C2
R2
C1
XOUT
XIN
SB16C1052PCI
XIN
XOUT
SB16C1052PCI
Optional
External
Clock
Output
Clock