DataSheet_SB16C1053APCI_v106
SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
46
11. UART(SB16C1050A) Functional Description
SB16C1050A offers 16C450 and 16C650 modes. When FIFO is enabled, it has a
register configuration compatible with 64-byte FIFO and 16C650, so it becomes
compatible with 16C650. If you enable 256-byte FIFO, you use the unique supreme
function that SB16C1050A offers. It offers communication speed up to 5.3Mbps and
more enhanced functions that other UARTs with 128-byte FIFO do not.
SB16C1050A can select hardware/software flow control. Hardware flow control
significantly reduces software overhead and increases system efficiency by
automatically controlling serial data flow using the RTS# output and CTS# input signals.
Software flow control automatically controls data flow by using programmable Xon/Xoff
characters.
UART I/O Space is determined by Base Address Register 0 (10h ~
13h) from PCI Configuration Space. This is BAR0 area of
Configuration Space and is for accessing actual physical UARTs.
11.1 UART I/O Address Map
8 bytes per Port are assigned since the type of installed UART is
16C550 compatible device.
Each BAR is assigned for each UART port in the SB16C1053APCI.
Each UART can be assigned each COM Port number. For
example, 1
st
UART Port can be assigned to COM11 and 2
nd
UART
Port can be assigned to COM15. But this port remap is not possible
in the 6S mode of SB16C1053APCI. Because BAR2 and BAR3
include each two UART ports in the space.
For more information, please refer ‘Table 8-6, Base Address
Registers’.
Table 11–1: UART I/O Address Map
BAR
I/O Address
1-serial Mode
2-serial Mode
BAR0
00 ~ 07h
UART0
UART0
BAR1
00 ~ 07h
-
UART1
11.1 FIFO Operation
SB16C1050A’s FIFO has two modes, 64-byte FIFO mode and 256-byte FIFO mode.
Setting FCR[0] to 1b enables FIFO, and if AFR[0] is set to 0b, it operates in 64-byte
FIFO mode(default). In this mode, Transmit Data FIFO, Receive Data and Receive
Status FIFO are 64 bytes. 64-byte FIFO mode allows you to select the Transmit
Interrupt Trigger Level from 8, 16, 32, or 56. You can verify this Interrupt Trigger Level
by TTR and RTR. In this mode TTR and RTR are Read Only.