DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
45
10.16 General Purpose Outputs Data Register (GPODR, BAR4+21h)
GPODR sets output value of GPO[1:0] respectively.
Table 10–15: General Purpose Outputs Data Register Description
Bit
Symbol
Description
1
GPODR[1]
The output value of GPO1 pin.
0
GPODR[0]
The output value of GPO0 pin.
Figure 10–3: GPO[1:0] outputs are controlled by GPOCR and GPODR
10.17 Parallel Additional Function Register (PAFR, BAR4+23h)
Controls the Host Logic High output pin and monitors Peripheral Logic High input pin.
Table 10–16: Parallel Additional Function Register Description
Bit
Symbol
Description
1
PAFR[1]
P_LOGIC_H : Peripheral Logic High
This bit indicates status of the peripheral device. (Read Only)
0b : It means the peripheral device isn’t in the stable status and
have some problems after power is supplied.
1b : It means the peripheral device is in the stable status after
power is supplied.
0
PAFR[0]
H_LOGIC_H : Host Logic High
This bit indicates status of the host device. (Read/Write)
When the host don’t go into the stable status and have some
problems after power is supplied, host output 0b through
H_LOGIC_H pin.
When the host goes into the stable status after power is supplied,
host output 1b through H_LOGIC_H pin.
GPO[0]
GPODR[0]
GPOCR[0]
GPO[1]
GPODR[1]
GPOCR[1]