DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
39
10.8 Interrupt Mask Register (IMR, BAR4+Ch)
IMR enables or disables interrupt of serial ports and parallel port.
Table 10–7: Interrupt Mask Register Description
Bit
Symbol
Description
7
IMR[7]
Not used.
6
IMR[6]
Interrupt Masking Bit for Parallel Port
0b: Disables Parallel Port interrupt. (default)
1b: Enables Parallel Port interrupt.
5
IMR[5]
Interrupt Masking Bit for 6
th
Serial Port
0b: Disables Serial Port6(4
th
external UART) interrupt. (default)
1b: Enables Serial Port6(4
th
external UART) interrupt.
4
IMR[4]
Interrupt Masking Bit for 5
th
Serial Port
0b: Disables Serial Port5(3
rd
external UART) interrupt. (default)
1b: Enables Serial Port5(3
rd
external UART) interrupt.
3
IMR[3]
Interrupt Masking Bit for 4
th
Serial Port
0b: Disables Serial Port4(2
nd
external UART) interrupt. (default)
1b: Enables Serial Port4(2
nd
external UART) interrupt.
2
IMR[2]
Interrupt Masking Bit for 3
rd
Serial Port
0b: Disables Serial Port3(1
st
external UART) interrupt. (default)
1b: Enables Serial Port3(1
st
external UART) interrupt.
1
IMR[1]
Interrupt Masking Bit for 2
nd
Serial Port
0b: Disables Serial Port2(2
nd
internal UART) interrupt. (default)
1b: Enables Serial Port2(2
nd
internal UART) interrupt.
0
IMR[0]
Interrupt Masking Bit for 1
st
Serial Port
0b: Disables Serial Port1(1
st
internal UART) interrupt. (default)
1b: Enables Serial Port1(1
st
internal UART) interrupt.