DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
35
10. Option I/O Space
Option I/O Space is determined by Base Address Register 4 (20h ~ 23h) from PCI Configuration Space.
Contents of I/O register which is installed in this area include basic information about PCI Multi Port hardware. The
size of this area is 64(00h ~ 3Fh) bytes total.
This Option Registers are made by SystemBase for users to control and manage Serial Multi-Port more easily and
conveniently. Users and software developers can easily control Serial Interface of Multi-Port with them.
Table 10-1: Option I/O Register Map
I/O Address
Register Name
I/O
00h
GIR0 (General Information Register 0 – Serial Port Number)
RO
01h
GIR1 (General Information Register 1 – Product Version)
RO
02h
GIR2 (General Information Register 2 – Parallel Port Number)
RO
03h
GIR3 (General Information Register 3 – PCI Core Version)
RO
03h
SRR (Software Reset Register)
WO
04h
DIR (Port1 ~ Port2, Device Information Register)
RO
05 ~ 07h
Reserved
-
08h
IIR0 (Port1 ~ Port2, Interface Information Register)
IIR0 (Port1, Interface Information Register) for ALL+ mode
RW
09h
IIR1 (Port2, Interface Information Register) for ALL+ mode
RW
0A ~ 0Bh
Reserved
-
0Ch
IMR (Port1 ~ Port2, Interrupt Mask Register)
RW
0D ~ 0Fhh
Reserved
-
10h
IPR (Port1 ~ Port2, Interrupt Poll Register)
RO
11 ~ 13h
Reserved
-
14h
PPFTTR (Parallel Port FIFO TX Threshold Register)
RW
15h
PPFRTR (Parallel Port FIFO RX Threshold Register)
RW
16h
ATPSR (Auto Toggle Pin Select Register)
RW
17h
PPISR (Parallel Port Interrupt Status Register)
RO
18h
PPMRR (PM_PME Message Resource Register in D3hot)
RW
19 ~ 1Bh
Reserved
-
1Ch ~ 1Fh
Reserved
-
20h
GPOCR (General Purpose Output Control Register)
RW
21h
GPODR General Purpose Output Data Register)
RW
22h
Reserved
-
23h
PAFR (Parallel Additional Function Register)
RW
24 ~ 3Fh
Reserved
-
Cf. RO – Read Only
WO – Write Only
RW – Read/Write