DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
18
Table 6–1: Pin Description…continued
I
2
C Serial EEPROM Interfaces
Name
Pin
Type
Description
SCL
52
O
Serial EEPROM Clock Output: Connected to SCL of serial EEPROM.
SDA
53
I/O
Serial EEPROM Data Input/Output: Connected to SDA of serial EEPROM.
PCI Interfaces
Name
Pin
Type
Description
CLK
118
I
PCI Clock: PCI clock provides timing for all transaction on SB16C1053APCI.
RST#
117
I
PCI Reset: Reset the SB16C1053APCI. The inputted signal indicates when
the applied main power is within the specified tolerance and stable. This signal
is asynchronous to CLK when asserted or deasserted.
INTA#
114
O/D
Interrupt A: Interrupt A is used to request an interrupt. Interrupts on PCI are
defined as “level sensitive”, asserted low, using open drain output drivers. The
assertion and deassertion of INTA# is asynchronous to CLK.
PME#
119
O/D
Power Management Event: This signal can be used by SB16C1053APCI to
request a change in the SB16C1053APCI or main system power state. The
assertion and deassertion of PME# is asynchronous to CLK. This signal has
additional electrical requirements over and above standard open drain signals
that allow it to be shared between devices that are powered off and those that
are powered on.
The use of this pin is specified in the PCI Bus Power Management Interface
Specification.
PMES_INTF02
56
I/O
This pin is dual mode pin. After power is supplied to the chip, the pin is set to
input mode for a while and receive INTFx[2:0] input. After that, the pin is set to
output mode and outputs PMES as Power Management Status.
PME Status: This signal indicates PM state. If PM state is in D0 state, it is set
to 1b and if PM state is in D3 state, it is cleared to 0b.
Line Interface Type Select: These pins are used to select the type of Line
Transceiver interfaced in Serial port Mode. The inputted value from these pins
is shown in IIR0[5:4] of the Option register.
PCI_33M#
61
I
PCI Operational Speed: This input is for selecting the operational speed of
PCI Bus. This chip is operated at 33MHz PCI Bus when this pin is cleared to
0b. And it is operated at 66MHz PCI Bus when this pin is setted to 1b.
PAR
23
T/S
Parity: Parity is even parity across AD[31:00] and C/BE[3:0]#.
FRAME#
13
S/T/S
Cycle Frame: This signal is driven by the master of main system to indicate
the beginning and duration of an access.
IRDY#
14
S/T/S
Initiator Ready: This signal indicates the initiating agent’s(main system’s)
ability to complete the current data phase of the transaction.
TRDY#
17
S/T/S
Target Ready: This signal indicates the target agent’s(SB16C1053APCI’s)
ability to complete the current data phase of the transaction.
STOP#
19
S/T/S
Stop: This signal indicates that the current target(SB16C1053APCI) is
requesting the master to stop current transaction.