DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
17
Table 6–1: Pin Description…continued
Function Configuration Interfaces
Name
Pin
Type
Description
DIR_INTF12_MA0
63
I/O
These pin are dual mode pin. After power is supplied to the chip, the pin is set
to input mode for a while and receive INTFx[2:0] input. After that, the pin is set
to output mode and outputs DIR or MA0. This pin works as DIR in 1P and
2S1P mode and MA0 of MIO Bus
TM
in 4S and 6S mode.
Parallel Port Direction: This pin indicates the data direction of parallel port
data. When it has ‘0’, it means forward direction. When it has ‘1’, it means
reverse direction.
MIO Bus Address Bus: This pin is the address bus of MIO Bus
TM
for external
UART channels.
Interface Setting: This pin is working in input mode for a while after power is
supplied to the chipset. In this time, interface setting is set and the value is
adopted to Interface Information Register in option register space.
PERILOGICH_MA
1_OSC1
62
I/O
This pin is dual mode pin. After power is supplied to the chip, the pin is set to
input mode for a while and receive OSCx[2:0] input. After that, the pin is set to
PERILOGICH(input) or MA1(output). This pin works as PERILOGICH in 1P
and 2S1P mode and MA1 of MIO Bus
TM
in 4S and 6S mode.
Parallel Port Peripheral Logic High: This input pin is set to indicate that the
peripheral is in valid state. But when this pin is reset to indicate that peripheral
is in power off state or invalid state.
MIO Bus Address Bus: This pin is the address bus of MIO Bus
TM
for external
UART channels.
Oscillator Setting 1: This pin is working in input mode for a while after power
is supplied to the chipset. In this time, oscillator setting is set and the value is
adopted to Device Information Register in option register space.
HOSTLOGICH_P
ORT2_MA2
59
I/O
This pin is dual mode pin. After power is supplied to the chip, the pin is set to
input mode for a while and receive PORTx[2:0] input. After that, the pin is set
to HOSTLOGICH(output) or MA2(output). This pin works as HOSTLOGICH in
1P and 2S1P mode and MA2 of MIO Bus
TM
in 4S and 6S mode.
Parallel Port Host Logic High: This output pin is set to indicate that the host
is in valid state. But when this pin is reset to indicate that host is in power off
state or invalid state.
MIO Bus Address Bus: This output pin is the address bus of MIO Bus
TM
for
external UART channels.
Port Setting 2: This input pin is a port setting for various operating modes.