SB16C1052PCI_Data Sheet_EN

SB16C1052PCI
PCI Target Interface Controller
with Dual UART
JULY 2013 REV 1.06
45
DLL and DLM must be written in order to program the baud rate. DLL and DLM are the
least and most significant byte of the baud rate divisor, respectively. If DLL and DLM are
both zero, the SB16C1050 is effectively disabled, as no baud clock will be generated.
Table 12–3 shows the baud rate and divisor value for prescaler with divide by 1 as well as
crystal with frequency 1.8432MHz, 3.6864MHz, 7.3728MHz, and 14.7456MHz,
respectively.
Figure 12–3 shows the crystal clock circuit reference.
Table 12–3: Baud Rates
Desired Baud Rate
16X Digit Divisor for Prescaler with Divide by 1
1.8432MHz
3.6864MHz
7.3728MHz
14.7456MHz
50
0900h
1200h
2400h
4800h
75
0600h
0C00h
1800h
3000h
150
0300h
0600h
0C00h
1800h
300
0180h
0300h
0600h
0C00h
600
00C0h
0180h
0300h
0600h
1200
0060h
00C0h
0180h
0300h
1800
0040h
0080h
0100h
0200h
2000
003Ah
0074h
00E8h
01D0h
2400
0030h
0060h
00C0h
0180h
3600
0020h
0040h
0080h
0100h
4800
0018h
0030h
0060h
00C0h
7200
0010h
0020h
0040h
0080h
9600
000Ch
0018h
0030h
0060h
19.2K
0006h
000Ch
0018h
0030h
38.4K
0003h
0006h
000Ch
0018h
57.6K
0002h
0004h
0008h
0010h
115.2K
0001h
0002h
0004h
0008h
230.4K
―
0001h
0002h
0004h
460.8K
―
―
0001h
0002h
921.6K
―
―
―
0001h