SB16C1052PCI_Data Sheet_EN

SB16C1052PCI
PCI Target Interface Controller
with Dual UART
JULY 2013 REV 1.06
44
12.4 Sleep Mode with Auto Wake-Up
The SB16C1050 provides sleep mode operation to reduce its power consumption when
sleep mode is activated. Sleep mode is enabled when EFR[4] and IER[4] are set to 1b.
Sleep mode is activated when:
■
■
■
■
RXD input is in idle state.
CTS#, DSR#, DCD#, and RI# are not toggling.
The TX FIFO and TSR are in empty state.
No interrupt is pending except THR and time-out interrupts.
In sleep mode, the SB16C1050 clock and baud rate clock are stopped. Since most
registers are clocked using these clocks, the power consumption is greatly reduced.
Normal operation is resumed when:
■
■
■
RXD input receives the data start bit transition.
Data byte is loaded to the TX FIFO or THR.
CTS#, DSR#, DCD#, and RI# inputs are changed.
12.5 Programmable Baud Rate Generator
The SB16C1050 has a programmable baud rate generator with a prescaler. The
prescaler is controlled by MCR[7], as shown in Figure 12–2. The MCR[7] sets the
prescaler to divide the clock frequency by 1 or 4. The baud rate generator further divides
this clock frequency by a programmable divisor (DLL and DLM) between 1 and (2
16
– 1)
to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is
used by transmitter for data bit shifting and receiver for data sampling.
The divisor of the baud rate generator is:
Divisor =
(
XTAL1 Crystal Input Frequency
)
Prescaler
(Desired Baud Rate x 16)
MCR[7] is cleared to 0b (prescaler = 1), when CLKSEL input is in high state after reset.
MCR[7] is set to 1b (prescaler = 4), when CLKSEL input is in low state after reset.
Figure 12–2: Prescaler and Baud Rate Generator Block Diagram
PROGAMMABLE
CLOCK
OSCILLATOR
LOGIC
LOGIC
DIVISOR
(DIVIDE BY 4)
MCR[7] = 0
BAUD RATE
XTAL2
REFERENCE
LOGIC
INTERNAL
(DIVIDE BY 1)
LOGIC
INTERNAL
BAUD RATE
CLOCK FOR
TRANSMITTER
AND
RECEIVER
PRESCALER
XTAL1
MCR[7] = 1
PRESCALER
GENERATOR