SB16C1052PCI_Data Sheet_EN

SB16C1052PCI
PCI Target Interface Controller
with Dual UART
JULY 2013 REV 1.06
4
12.5 Programmable Baud Rate Generator .................................................................................... 44
12.6 Break and Time-out Conditions ............................................................................................ 46
13. Register Descriptions ................................................................................................................... 47
13.1 Transmit Holding Register (THR, Page 0) .............................................................................. 51
13.2 Receive Buffer Register (RBR, Page 0) .................................................................................. 51
13.3 Interrupt Enable Register (IER, Page 0) ................................................................................ 52
13.4 Interrupt Status Register (ISR, Page 0) ................................................................................ 53
13.5 FIFO Control Register (FCR, Page 0) .................................................................................... 54
13.6 Line Control Register (LCR, Page 0) ...................................................................................... 55
13.7 Modem Control Register (MCR, Page 0) ................................................................................ 56
13.8 Line Status Register (LSR, Page 0) ....................................................................................... 57
13.9 Modem Status Register (MSR, Page 0) ................................................................................. 58
13.10 Scratch Pad Register (SPR, Page 0) .................................................................................... 58
13.11 Divisor Latches (DLL, DLM, Page 1) .................................................................................... 58
13.12 Transmit FIFO Count Register (TCR, Page 2) ....................................................................... 59
13.13 Receive FIFO Count Register (RCR, Page 2) ........................................................................ 59
13.14 Flow Control Status Register (FSR, Page 2) ......................................................................... 59
13.15 Page Select Register (PSR, Page 3) .................................................................................... 61
13.16 Auto Toggle Control Register (ATR, Page 3) ........................................................................ 62
13.17 Enhanced Feature Register (EFR, Page 3) ........................................................................... 63
13.18 Additional Feature Register (AFR, Page 4) ........................................................................... 64
13.19 Xoff Re-transmit Count Register (XRCR, Page 4).................................................................. 64
13.20 Transmit FIFO Trigger Level Register (TTR, Page 4) ............................................................. 64
13.21 Receive FIFO Trigger Level Register (RTR, Page 4) .............................................................. 64
13.22 Flow Control Upper Threshold Register (FUR, Page 4) ......................................................... 65
13.23 Flow Control Lower Threshold Register (FLR, Page 4) .......................................................... 65
14. Programmer’s Guide .................................................................................................................... 67
15. Electrical Information ................................................................................................................... 72
15.1 Absolute Maximum Ratings ............................................................................................... 72
15.2 Power Consumption .......................................................................................................... 72
15.3 DC Characteristics ............................................................................................................. 72
15.3.1 PCI PAD 3.3V 66MHz DC Signaling Characteristics ....................................................... 72
15.3.1 PCI PAD 3.3V 66MHz DC Signaling Characteristics ....................................................... 72
16. Timing Specification .................................................................................................................... 73