SB16C1052PCI_Data Sheet_EN

SB16C1052PCI
PCI Target Interface Controller
with Dual UART
JULY 2013 REV 1.06
33
11.10 PME# Signal Resource Register (PSRR)
Select event signal to wakeup Root Complex in D3
hot
state.
Table 11–8: PME# Signal Resource Register Description
Bit
Symbol
Description
1
PSRR[1]
0b: Interrupt is not selected as Wakeup Event for waking up Root Complex (default).
1b: Interrupt is selected as Wakeup Event for waking up Root Complex.
Whether interrupt is generated or not is determined by IMR. That is, some port can only
generate interrupt or any ports among all ports can generate interrupt. When interrupt
occurs, asserts PME# signal to Root Complex.
0
PSRR[0]
0b: WAKEREQ pin is not selected as Wakeup Event for waking up Root Complex
(default).
1b: WAKEREQ pin is selected as Wakeup Event for waking up Root Complex.
When 1b is received by any logic, asserts PME# signal to Root Complex.
If PSRR[1:0] is set as 11b which means both D3
hot
-Interrupt and D3
hot
-WAKEREQ are
set, PME# signal is asserted when only one of both events occurs.
11.11 SystemBase ID Register 0 (SIR0)
Hardwired to 53h (“S” of SystemBase).
11.12 SystemBase ID Register 1 (SIR1)
Hardwired to 42h (“B” of SystemBase).
11.13 Chip ID Register (CIR)
Hardwired to 43h.
It indicates SB4003 series.
11.14 (Chip Revision Register (CRR)
Hardwired to 10h.
It indicates Revision 1.0 of SB16C1052PCI.