SB16C1052PCI_Data Sheet_EN

SB16C1052PCI

PCI Target Interface Controller

with Dual UART

JULY 2013 REV 1.06

11.2 General Information Register1 – Product Version (GIR1)

General Information Register1 indicates the version of PCI Target Controller. (Currently B0h meaning

B.0)

11.3 General Information Register2 – Sub-Product Version (GIR2)

General Information Register2 indicates the sub-product the version of PCI Target Controller.

Sub-Product Version = 00h means Serial 1-port mode

Sub-Product Version = 01h means Serial 2-port mode

Sub-Product Version = 80h means Serial 1-port ALL mode

Sub-Product Version = 81h means Serial 2-port ALL mode

11.4 General Information Register3 – Core Version (GIR3)

General Information Register3 indicates SystemBase’s PCI Target Interface Core version (Currently

24h meaning 2.4)

11.5 Software Reset Register

If 52h(“R”) is written on SRR, Reset is outputted to Serial Multi-Port I/O Bus and this means PCI UART

goes to Reset state. If values other than 52h are written on SRR, Reset state is cleared.

11.6 Device Information Register (DIR)

DIR: Device information of Port1 ~ Port2

Table 11–2: Device Information Register Description

Bit

Symbol

Description

7:4

DIR[7:4]

UART Select: Content of U[2:0] shows type of UART.

000b: 16C550 compatible UART

001b: 16C1050 (Default)

010 ~ 111b: Not supported

3:0

DIR[3:0]

Oscillator Frequency Select: O[3:0] shows frequency

(maximum communication speed) of communication modification

sender that is used.

0000b: 1.8432MHz (115.2Kbps)

0001b: 3.6864MHz (230.4Kbps)

0010b: 7.3728MHz (460.8Kbps)

0011b: 14.7456MHz (921.6Kbps)

0100b: 29.4912MHz (1,8432.2Kbps)

0101b: 58,9842MHz (3,6864.4Kbps)

0110 ~ 1111b: Not supported