SB16C1052PCI_Data Sheet_EN

SB16C1052PCI
PCI Target Interface Controller
with Dual UART
JULY 2013 REV 1.06
14
Table 6–1: Pin Description…continued
Name
Pin
Type
Description
AD[31], AD[30]
AD[29], AD[28]
AD[27], AD[26]
AD[25], AD[24]
AD[23], AD[22]
AD[21], AD[20]
AD[19], AD[18]
AD[17], AD[16]
AD[15], AD[14]
AD[13], AD[12]
AD[11], AD[10]
AD[09], AD[08]
AD[07], AD[06]
AD[05], AD[04]
AD[03], AD[02]
AD[01], AD[00]
24, 25
26, 29
30, 31
32, 33
36, 39
40, 41
42, 43
44, 45
61, 62
63, 64
65, 66
67, 68
72, 73
74, 75
76, 77
78, 79
T/S
Address and Data: These signals are multiplexed on the same pins. A Bus
transaction consists of an address phase followed by a data phase.
SB16C1052PCI does no support both read and write bursts.
C/BE[3]#
C/BE[2]#
C/BE[1]#
C/BE[0]#
34
46
58
71
T/S
Bus Command and Byte Enables: These signals are multiplexed on same
pins. During the address phase of transaction, C/BE[3:0]# define the bus
command. During the data phase, C/BE[3:0]# are used as Byte Enables.
PAR
57
T/S
Parity: Parity is even parity across AD[31:00] and C/BE[3:0]#.
FRAME#
47
S/T/S
Cycle Frame: This signal is driven by the master of main system to indicate
the beginning and duration of an access.
IRDY#
50
S/T/S
Initiator Ready: This signal indicates the initiating agent’s(main system’s)
ability to complete the current data phase of the transaction.
TRDY#
51
S/T/S
Target Ready: This signal indicates the target agent’s(SB16C1052PCI’s)
ability to complete the current data phase of the transaction.
STOP#
53
S/T/S
Stop: This signal indicates that the current target(SB16C1052PCI) is
requesting the master to stop current transaction.
LOCK#
54
S/T/S
Lock: This signal provides for exclusive use of a resource. SB16C1052PCI
may be locked by one master at a time. See the PCI Local Bus Specification
for the detail operation of lock function.
IDSEL
35
I
Initialization Device Select: This is used for chip selection during
configuration read and write transaction.
DEVSEL#
52
S/T/S
Device Select: This signal indicates that the driving device has decoded its
address as the target of the current access. As an input, DEVSEL# indicates
whether any device on the bus has been selected.
PERR#
55
S/T/S
Parity Error: This signal is only for reporting data parity errors during all PCI
transactions except Special Cycle.
SERR#
56
S/T/S
System Error: This signal is for reporting address parity errors, data parity
errors on the Special Cycle command, or any other system error where the
result will be catastrophic.