Manualshelf

SB16C1052PCI_Data Sheet_EN

ManualsBrandsSystemBase ManualsElectronic ComponentsPCI to Dual UART with 256 Byte FIFO Bridge Controller - 90pcs Bundle
11121314151617181920
SB16C1052PCI
PCI Target Interface Controller
with Dual UART
JULY 2013 REV 1.06
13
Table 6–1: Pin Description…continued
Name
Pin
Type
Description
GPIO[7]
GPIO[6]
GPIO[5]
GPIO[4]
GPIO[3]
GPIO[2]
GPIO[1]
GPIO[0]
108
109
110
111
114
115
116
117
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General Purpose Input and Output: These pins are controlled by GOER,
GOR, GIR of the Option register.
TRXSEL[1]
TRXSEL[0]
87
88
I
I
Auto Toggling Signal Select: These pin select the signal for auto toggling in
RS422 or RS485 driving.
TRXSEL[1:0] = 00b : RTSx# signal is selected.
TRXSEL[1:0] = 01b : DTRx# signal is selected.
TRXSEL[1:0] = 10b : TXENx, RXENx# signals are selected.
Serial EEPROM Interfaces
Name
Pin
Type
Description
RCS
86
O
Serial EEPROM Chip Select: Connected to CS of serial EEPROM.
RSK
85
O
Serial EEPROM Data Clk: Connected to SK of serial EEPROM.
RDI
83
I
Serial EEPROM Data Input: Connected to DO of serial EEPROM.
RDO
84
O
Serial EEPROM Data Output: Connected to DI of serial EEPROM.
PCI Interfaces
Name
Pin
Type
Description
CLK
21
I
PCI Clock: PCI clock provides timing for all transaction on SB16C1052PCI.
RESET#
19
I
PCI Reset: Reset the SB16C1052PCI. The inputted signal indicates when the
applied main power is within the specified tolerance and stable. This signal is
asynchronous to CLK when asserted or deasserted.
INTA#
18
O/D
Interrupt A: Interrupt A is used to request an interrupt. Interrupts on PCI are
defined as “level sensitive”, asserted low, using open drain output drivers. The
assertion and deassertion of INTA# is asynchronous to CLK.
PME#
23
O/D
Power Management Event: This signal can be used by SB16C1052PCI to
request a change in the SB16C1052PCI or main system power state. The
assertion and deassertion of PME# is asynchronous to CLK. This signal has
additional electrical requirements over and above standard open drain signals
that allow it to be shared between devices that are powered off and those that
are powered on.
The use of this pin is specified in the PCI Bus Power Management Interface
Specification.