SB16C1052PCI_Data Sheet_EN

SB16C1052PCI
PCI Target Interface Controller
with Dual UART
JULY 2013 REV 1.06
10
6. Pin Configuration
6.1 Pin Configuration for 128-Pin TQFP Package
Figure 6–1: 128-Pin TQFP Pin Configuration
WAKEREQ
INTF0[0]
OSC[2]
PERR#
C/BE[0]#
XOUT
C/BE[3]#
FRAME#
70
89
RESET#
AD[31]
56
105
5
1
CTS0#
NC - No internal connection
GND
79
GND
3
54
DSR0#
100
GND
PORT_SEL
GND
OSC[0]
VCC
AD[15]
32
CLK
AD[23]
118
66
72
GND
108 121
59
99
14
17
AD[01]
INTF0[1]
87
TXEN0
LOCK#
GPIO[6]
28
NC
AD[10]
AD[04]
INTF1[0]
AD[16]
VCC
22
GND
AD[29]
77
103
64
83
88
RDI
VCC
RXEN0#
VCC
GND
GPIO[5]
35 58 42
120
97
33
95
36
74
GPIO[1]
112
18
126
GND
AD[19]
AD[09]
TRXSEL[0]
13
117
GPIO[7]
82
34
16
11
6
109
61
15
55
123
AD[24]
AD[08]
RDO
85
TXD1
VCC
AD[25]
50
ALL_EN
CLKSEL
GND
AD[28]
AD[17]
65
26
TXD0
86
119 110
62
VCC
78
124 115
23
94
AD[13]
2
DCD1#
AD[14]
76
57 51 41
122
60
EXT_LOAD
RCS
TRXSEL[1]
12
RI0#
VCC
AD[30]
63
8
113
10
102
GPIO[3]
127
92
GND
AD[06]
RXEN1#
INTA#
GND
68
30
47
98
107 111
27
53
24
125
DTR0#
C/BE[1]#
RSK
DEVSEL#
IRDY#
AD[21] AD[20]
29
RXD1
PME#
AD[27]
81
106
69
9
45 40
128
49
25
114
52 37
104
71
XIN
VCC
AD[05]
AD[03]
AD[02]
VCC
IDSEL
PAR
7
91
RI1#
TXEN1
SB16C1052PCI-TQ
4
19
21
GPIO[0]
RXD0
93
38
20
VCC
48
GND
OSC[1]
C/BE[2]#
STOP#
DSR1#
VCC
AD[22]
96
RTS1#
VCC
AD[07]
PME_S
SERR#
AD[11]
GND
GND
AD[18]
116
DTR1#
GND
67
31
75
46
GPIO[4]
84
73
39
90
43
RTS0# GPIO[2]
44
DCD0#
AD[12]
GND
AD[00]
CTS1#
AD[26]
TRDY#
101
80
INTF1[1]