SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 PCI Target Interface Controller SB16C1052PCI Revision 1.06 SystemBase Co., Ltd.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 CONTENTS 1. Description ..................................................................................................................................... 6 2. Features ......................................................................................................................................... 6 2.1 PCI Interface .....................................................................................................
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 8.2.2 Pointer to Next Capability (41h).................................................................................... 23 8.2.3 Power Management Capabilities (42~43h) .................................................................... 23 8.2.4 Power Management Control/Status Register (44~45h) ................................................... 24 9. Power Management .........................................................
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 12.5 Programmable Baud Rate Generator .................................................................................... 44 12.6 Break and Time-out Conditions ............................................................................................ 46 13. Register Descriptions ................................................................................................................... 47 13.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 16.1 PCI BUS Timing Specifications ............................................................................................. 73 17. Package Outline ...........................................................................................................................
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 1. Description SB16C1052PCI is a PCI Target Interface Controller with Dual-UART. It offers easy PCI Target Card Adapter implementation. SB16C1052PCI provides high performance serial communication. With a built-in Dual-SB16C1050 Core that has built-in 256-byte FIFO, SB16C1052PCI decreases CPU load, is stronger at errors such as Overrun error and works well with simultaneous use of multiple ports.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 ■ Optional Data Flow Additional Halt by Xoff Re-transmit Control ■ Control pins for RS-422 Point to Point/Multi-Drop Auto Control ■ Control pins for RS-485 Echo/Non Echo Auto Control ■ Software Selectable Baud Rate Generator ■ Prescaler Provides Additional Divide-by-4 Function ■ Programmable Sleep Mode ■ Programmable Serial Interface Characteristics REV 1.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 4.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 5. Applications 5.1 Serial 1-port Serial 1-port is generally made with SB16C1052PCI (called by Serial 1-port Mode). Special logic is not needed to make one serial port since Single-UART is built inside the SB16C1052PCI. Depending on Serial Interface, Transceiver IC of the RS232, RS422 or RS485 needs to be attached for long distance transmission.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 6.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 6.2 Pin Description Table 6–1: Pin Description Modem and Serial I/O Interface Name Pin Type Description TXD0 120 O Transmit Data: These pins are individual transmit data output. During the TXD1 4 O local loop-back mode, the TXD output pin is disabled and TXD data is internally connected to the RXD input. RXD0 125 I Receive Data: These pins are individual receive data input.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 Table 6–1: REV 1.06 Pin Description…continued Name Pin Type Description PORT_SEL 89 I Port Select: These pins are used to select the operating mode of SB16C1052PCI from Serial 1-port Mode, Serial 2-port Mode. PORT = 0b : Serial 1-port Mode is selected. (1P) PORT = 1b : Serial 2-port Mode is selected.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 Table 6–1: REV 1.06 Pin Description…continued Name Pin Type Description GPIO[7] 108 I/O General Purpose Input and Output: These pins are controlled by GOER, GPIO[6] GPIO[5] 109 110 I/O I/O GOR, GIR of the Option register.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 Table 6–1: Pin Description…continued Name Pin Type Description AD[31], AD[30] AD[29], AD[28] 24, 25 26, 29 T/S Address and Data: These signals are multiplexed on the same pins. A Bus transaction consists of an address phase followed by a data phase.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 Other Interfaces Name Pin Type Description XIN 96 I Crystal or External Clock Input: This input of up to 85MHz for data rate of 5.3Mbps at 3.3V. XOUT 95 O Crystal or Buffed Clock Output: This output level is 3.3V. WAKE_REQ 107 I WAKE Request: PM state of PCI Device goes from D3 state to D0 state with the Wake Up Event.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 7. Configuration Loader SB16C1052PCI can perform system initialization by reading PCI Configuration header data from Internal MIO registers or external serial EEPROM. It is decided through EXT_LOAD pin and describes configuration information of each MIO registers or external serial EEPROM.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 Table 7–2: Serial EEPROM Information Table Address Description 00h Vendor ID Low Byte 01h Vendor ID High Byte 02h Device ID Low Byte 03h Device ID High Byte 04h Revision ID 05h Class Code Low Byte 06h Class Code Middle Byte 07h Class Code High Byte 08h Sub Vendor ID Low Byte 09h Sub Vendor ID High Byte 0Ah Sub System ID Low Byte 0Bh Sub System ID High Byte 0Ch~ REV 1.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 8. PCI Configuration Space PCI Configuration offers one type of Configuration Space access method. - PCI Compatible Configuration method PCI Compatible Configuration method is compatible with PCI version 2.3 and higher and supports 100% binary compatibility to software for operating system agreed bus list and organization. From 0 byte up to 256 bytes is called PCI Compatible Configuration Space 8.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 8.1.1 Vendor ID A 16-bit register which represents the manufacturer of the device. It is a unique ID given by PCI SIG after membership registration. If you do not own a Vendor ID, it is fine to use 14A1h given to SystemBase by PCI SIG. 8.1.2 Device ID A 16-bit unique ID of each device given by the Function Manufacturer which can be assigned by the manufacturer freely. It is related to software driver installation/recognition.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 8.1.4 Status Register Table 8–3: Status Register Bit Type 15 RW 14 RW 13 RW Description Detected Parity Error: This bit must be set by the device whenever it detects a parity error, even if parity error handling is disabled. Default value of this bit is 0b. Signaled System Error: This bit must be set whenever the device asserts SERR#. Devices that will never assert SERR# do not need to implement this bit.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 8.1.5 Revision This register shows device revision. Manufacturer can assign it freely. It is also related to software device driver installation. 8.1.6 Class Code This register contains descriptions on functions the device implements. It is divided as Base Class, Sub Class and Programming Interface in bytes. It must be set to the values provided by PCI Bus Specification.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 8.1.11 Base Address Registers These are spaces for assigning Base address for accessing I/O device or memory on PCI Local Bus. There are 6 spaces from Base Address Register 0 to 5, but spaces from Base Address Register 2 to 5 are set as unused reserved area. In SB16C1052PCI, Base Address Register 0 is used for UART and Base Address Register 1 is used for Option Registers.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 8.2 Power Management Registers of SB16C1052PCI Sometimes control over power is needed on PCI Bus applied systems. Especially in cases when system uses independent power source like mobile system or when PCI device uses a lot of power, the system must limit power supply to PCI device when it is not in use to make a power efficient system.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 8.2.4 Power Management Control/Status Register (44~45h) This 16bit Register manages PCI Function’s Power Management state and it is also used to enable and monitor PME. Table 8–8: Power Management Control/Status Register Bit Type Description 15 RW PME_Status: This bit is set when the function would assert the PME# signal independent of the state of the PME_En bit.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 9. Power Management PCI was the most famous and useful bus since it was introduced in 1992. It is used in various computer systems from Laptops to Servers. It supported high performance applications by offering large bandwidth and efficiently supporting multiple masters. Also, it offers efficient power management through Power Management and various types of Form Factor modules and Applications.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 Power On Reset D0 Uninitialized PCI RST# Sof t Reset D0 Active D2 D3cold D1 Figure 9–1: D3 hot Vcc Remov ed PCI Function Power Management State Transition Cf. Hibernate state is variation of shutdown state. In this state, all states of computer is saved on disk and thus when power comes back, it can be started as current session. 9.2 SB16C1052PCI Power Management Pins and Functions 9.2.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 Below figure is Logic Diagram of MAX3243. As you can see from this figure, RIN2 input signal (this pin is mainly prepared to be used by Ring Indicator.) is forked to reversed output signal called ROUT2 and output called ROUT2B. Among these, ROUT2B signal is not influenced by FORCEOFF# FORCEOFF# signal and input/output of buffer is Auto-power down FORCEON not restricted.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 10. UART I/O Space UART I/O Space is determined by Base Address Register 0 (10h ~ 13h) from PCI Configuration Space. This is BAR0 area of Configuration Space and is for accessing actual physical UARTs. 10.1 UART I/O Address Map 8 bytes per Port are assigned since the type of installed UART is 16C550 compatible device. I/O area of BAR0 increased with number of port.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 11. Option I/O Space Option I/O Space is determined by Base Address Register 1 (14h ~ 17h) from PCI Configuration Space. Contents of I/O register which is installed in this area include basic information about PCI Multi Port hardware. The size of this area is 32(00h ~ 1Fh) bytes total. This Option Registers are made by SystemBase for users to control and manage Serial Multi-Port more easily and conveniently.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 11.2 General Information Register1 – Product Version (GIR1) General Information Register1 indicates the version of PCI Target Controller. (Currently B0h meaning B.0) 11.3 General Information Register2 – Sub-Product Version (GIR2) General Information Register2 indicates the sub-product the version of PCI Target Controller.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 11.7 Interface Information Register0 ~ 1 (IIR0 ~ 1) IIR0 indicates interface information for Serial 1-port mode, Serial 1-port ALL mode, Serial.2-port mode, and 1’st port of Serial 2-port ALL mode. IIR1 indicates interface information for 2’nd port of Serial 2-port ALL mode.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 11.8 Interrupt Mask Register (IMR) IMR enables or disables interrupt of Serial 1, 2-port mode. Table 11–6: Interrupt Mask Register Description Bit Symbol Description 7 IMR[7] Not used. 6 IMR[6] Not used. 5 IMR[5] Not used. 4 IMR[4] Not used. 3 IMR[3] Not used. 2 IMR[2] Not used. 1 IMR[1] 0b: Disables Port2 interrupt on Serial 2-port mode, and Serial 2-port ALL mode.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 11.10 PME# Signal Resource Register (PSRR) Select event signal to wakeup Root Complex in D3hot state. Table 11–8: PME# Signal Resource Register Description Bit Symbol Description 1 PSRR[1] 0b: Interrupt is not selected as Wakeup Event for waking up Root Complex (default). 1b: Interrupt is selected as Wakeup Event for waking up Root Complex. Whether interrupt is generated or not is determined by IMR.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 11.10 GPIO Output Enable Register (GOER) GOER enables or disables GPIO[7:0] to output ports respectively. Table 11–9: GPIO Output Enable Register Description Bit Symbol Description 7 GOER[7] 0b: GPIO[7] is selected to input port (default). 1b: GPIO[7] is selected to output port. 6 GOER[6] 0b: GPIO[6] is selected to input port (default). 1b: GPIO[6] is selected to output port.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 11.12 GPIO Input Register (GIR) Reads input of GPIO[7:0] respectively. Table 11–11: GPIO Input Register Description Bit Symbol Description 7 GIR[7] Reads the input of GPIO[7]. 6 GIR[6] Reads the input of GPIO[6]. 5 GIR[5] Reads the input of GPIO[5]. 4 GIR[4] Reads the input of GPIO[4]. 3 GIR[3] Reads the input of GPIO[3]. 2 GIR[2] Reads the input of GPIO[2]. 1 GIR[1] Reads the input of GPIO[1].
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 12. UART(SB16C1050) Functional Description SB16C1050 offers 16C450 and 16C650 modes. When FIFO is enabled, it has a register configuration compatible with 64-byte FIFO and 16C650, so it becomes compatible with 16C650. If you enable 256-byte FIFO, you use the unique supreme function that SB16C1050 offers. It offers communication speed up to 5.3Mbps and more enhanced functions that other UARTs with 128-byte FIFO do not.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 retransmitted because external device has reported that it can accept more data. These operations prevent overrun during communication and if hardware flow control is disabled and transmit data rate exceeds RX FIFO service latency, overrun error occurs. 12.2.1 Auto-RTS To enable Auto-RTS, EFR[6] should be set to 1b. Once enabled, RTS# outputs 0b.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 12.2.2 Auto-CTS Setting EFR[7] to 1b enables Auto-RTS. If enabled, data in TX FIFO are determined to be transmitted or suspended by the value of CTS#. If 0b, it means external UART can receive new data and data in TX FIFO are transmitted through TXD pin. If 1b, it means external UART can not accept more data and data in TX FIFO are not transmitted. But data being transmitted by then complete transmission.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 12.3 Software Flow Control Software flow control is performed by Xon and Xoff character transmitting/accepting. Software flow control is enabled/disabled independently by programming EFR[3:0] and MCR[6:5, 2]. If TX software flow control is enabled by EFR[3:2], Xoff character is transmitted to report that data can not be accepted when the stored amount of data in RX FIFO exceeds the value in FUR.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 12.3.1 Transmit Software Flow Control To make Transmit Software Flow Control enabled, EFR[3:2] must be set to 01b, 10b or 11b. Unlike Auto-RTS in which 0b is outputted on RTS# when TX software flow control function is enabled, Xon character is not transmitted at first. If the amount of data in RX FIFO (written in ISR[6] and RCR) is less than the value in FUR, Xon character is not transmitted because Xon is in initial state.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 character. ■ If Xon and Xoff character are set to same, both characters are treated as Xon character. Tips for using Xon/Xoff character as two characters are as follows. ■ If received characters are Xon1, Xon1 and Xon2, RX flow control status becomes XON and previous Xon1 is ignored. ■ If received characters are Xoff1, Xoff1 and Xoff2, RX flow control status becomes XOFF and previous Xoff1 is ignored.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 Table 12–2: Xon/Xoff Character Recognition Logic Table Xon1 Char. Xon2 Char. Xoff1 Char. Xoff2 Char. Recognition of Recognition of 11h 11h 13h 13h Xon Char. Xoff Char.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 12.3.3 Xon Any Function While RX Software flow control function is enabled, data in TX FIFO are transmitted when received Xon character and transmission is suspended when Xoff character is received. This status is called ‘XOFF status’. Transmission is re-started when status changes to ‘XON status’ by incoming Xon character or Xon Any function that changes status when any data arrives.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 12.4 Sleep Mode with Auto Wake-Up The SB16C1050 provides sleep mode operation to reduce its power consumption when sleep mode is activated. Sleep mode is enabled when EFR[4] and IER[4] are set to 1b. Sleep mode is activated when: ■ RXD input is in idle state. ■ CTS#, DSR#, DCD#, and RI# are not toggling. ■ The TX FIFO and TSR are in empty state. ■ No interrupt is pending except THR and time-out interrupts.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 DLL and DLM must be written in order to program the baud rate. DLL and DLM are the least and most significant byte of the baud rate divisor, respectively. If DLL and DLM are both zero, the SB16C1050 is effectively disabled, as no baud clock will be generated. Table 12–3 shows the baud rate and divisor value for prescaler with divide by 1 as well as crystal with frequency 1.8432MHz, 3.6864MHz, 7.3728MHz, and 14.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 External Clock XIN XIN SB16C1052PCI Optional Clock Output R1 R2 XOUT XOUT C1 Figure 12–3: Table 12–4: SB16C1052PCI CRYSTAL C2 Crystal Clock Circuit Reference Diagram Component Values Frequency Range (MHz) C1 (pF) C2 (pF) R1 (Ω) R2(Ω) 3.6~8 22 68 220K 470 ~ 1.5K 8~16 33~68 33 ~ 68 220K ~ 2.2M 470 ~ 1.5K 12.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 TX FIFO TSR Output M S R Character #2 Character #1 16X Clock L S R MCR[6] = 0 M S R Transmitter Shift Register(TSR) M S R MCR[6] = 1 Brake Condition Output L S R MCR[6] = 0 L S R MCR[6] = 0 TXD PIN MCR[6] = 1 Figure 12–4: Break Condition Block Diagram 13.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 Table 13–1: Address REV 1.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 Table 13–1: REV 1.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 Table 13–2: Addr. A[2:0] Reg. REV 1.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 Table 13–2: Addr. A[2:0] REV 1.06 Internal Registers Description…continued Reg.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 13.3 Interrupt Enable Register (IER, Page 0) IER enables each of the seven types of Interrupt, namely receive data ready, transmit empty, line status, modem status, Xoff received, RTS# state transition from low to high, and CTS# state transition from low to high. All interrupts are disabled if bit[7:0] are cleared. Interrupt is enabled by setting appropriate bits. Table 13–3 shows IER bit settings.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 13.4 Interrupt Status Register (ISR, Page 0) The UART provides multiple levels of prioritized interrupts to minimize software work load. ISR provides the source of interrupt in a prioritized manner. Table 13–4 shows ISR[7:0] bit settings. Table 13–4: Interrupt Status Register Description Bit Symbol Description 7 ISR[7] FCR[0]/256 TX FIFO Empty: When 256-byte FIFO mode is disabled (default). Mirror the content of FCR[0].
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 13.5 FIFO Control Register (FCR, Page 0) FCR is used for enabling the FIFOs, clearing the FIFOs, setting transmit/receive FIFO trigger level, and selecting the DMA modes. Table 13–5 shows FCR bit settings.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 13.6 Line Control Register (LCR, Page 0) LCR controls the asynchronous data communication format. The word length, the number of stop bits, and the parity type are selected by writing the appropriate bits to the LCR. Table 13–6 shows LCR bit settings. Table 13–6: Line Control Register Description Bit Symbol Description 7 LCR[7] Divisor Latch Enable: 0b: Disable the divisor latch (default). 1b: Enable the divisor latch.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 13.7 Modem Control Register (MCR, Page 0) MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem. Table 13–7 shows MCR bit settings. Table 13–7: Modem Control Register Description Bit Symbol Description 7 MCR[7] Clock Prescaler Select: 0b: Divide by 1 clock input (default). 6 MCR[6] 1b: Divide by 4 clock input.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 13.8 Line Status Register (LSR, Page 0) LSR provides the status of data transfers between the UART and the CPU. When LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX FIFO. The errors in a character are identified by reading LSR and then reading RBR. Reading LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO read pointer is incremented by reading the RBR.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 13.9 Modem Status Register (MSR, Page 0) MSR provides the current status of control signals from modem or auxiliary devices. MSR[3:0] are set to 1b when input from modem changes and cleared to 0b as soon as CPU reads MSR. Table 13–9 shows MSR bit settings. Table 13–9: Modem Status Register Description Bit Symbol Description 7 MSR[7] DCD Input Status: Complement of Data Carrier Detect (DCD#) input.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 13.12 Transmit FIFO Count Register (TCR, Page 2) TCR shows the number of characters that can be stored in TX FIFO. In 64-byte FIFO mode, it consists of only TCR[6:0]. If the number of characters that can be stored in TX FIFO is 0, it is shown as 0000_0000b and if 64, it is shown as 0100_0000b. In 256-byte FIFO mode, it consists of ISR[7] + TCR[7:0].
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 less than the value of FUR, or it means the number of data in RX FIFO was more than the value of FUR and after the CPU read them, the number of data that remains unread after the CPU read the data received in RX FIFO is less than or equal to the value of FLR. That is, UART transmits Xon character to report external device that it can receive more data.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 13.15 Page Select Register (PSR, Page 3) If BFh is written in LCR, registers in Page3 and Page4 can be accessed. PSR is used to determine which page to use. Table 13–11 shows PSR bit settings. Table 13–11: Page Select Register Description Bit Symbol Description 7:1 PSR[7:1] Access Key: When writing data on PSR to change page, Access Key must be correspondent.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 13.16 Auto Toggle Control Register (ATR, Page 3) ATR controls the signals for controlling input/output signals when using Line Interface as RS422 or RS485, so eliminates additional glue logic outside. Table 13–12 shows ATR bit settings. Table 13–12: Auto Toggle Control Register Description Bit Symbol Description 7 ATR[7] RXEN# Polarity Select: 0b: Asserted output of RXEN# is 0b. 1b: Asserted output of RXEN# is 1b.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 13.17 Enhanced Feature Register (EFR, Page 3) EFR enables or disables the enhanced features of the UART. Table 13–13 shows EFR bit settings. Table 13–13: Enhanced Feature Register Description Bit Symbol Description 7 EFR[7] Auto-CTS Flow Control Enable: 0b: Auto-CTS flow control is disabled (default). 1b: Auto-CTS flow control is enabled. Transmission stops when CTS# pin is inputted 1b.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 13.18 Additional Feature Register (AFR, Page 4) AFR enables or disables the 256-byte FIFO mode and controls the global interrupt. Table 13–14 shows AFR bit settings. Table 13–14: Additional Feature Register Description Bit Symbol Description 7:6 AFR[7:1] Not used, always 000_0000b.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 13.22 Flow Control Upper Threshold Register (FUR, Page 4) FUR can be written only when 256-byte FIFO mode is enabled and one of TX software flow control or Auto-RTS is enabled (In 64-byte mode, it cannot be written but can be read only, and follows the value of trigger level set in FCR[5:4]). While TX software flow control is enabled, Xoff character is transmitted when the number of data in RX FIFO exceeds the value of FUR.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 14. Programmer’s Guide The base set of registers that is used during high-speed data transfer has a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide will help with programming these registers. Note that the descriptions below are for individual register access.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 Table 14–1: REV 1.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 Table 14-2: SB16C1052PCI Programming Guide Command Action Initialize Process 1. Set Baud Rate to 0001h Read LCR, then save in temp Set LCR to 80h Set DLL to 01h Set DLM to 00h Set LCR to temp 2. Set TTR to 20h Set LCR to BFh Set PSR to A5h Set TTR to 20h 3. Set RTR to 80h Set RTR to 80h 4. Enable 256-byte FIFO Set AFR to 01h 5.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 5. Read Data Read TX_Data from TX_User_Buffer 6. Output TX Set THR to TX_Data Table 14-2: SB16C1052PCI Programming Guide…continued Command Action Else For (Cnt = 0; Cnt < temp3; Cnt++) 5. Read Data Read TX_Data from TX_User_Buffer 6. Output TX Set THR to TX_Data Return from Interrupt Service Routine Serial Input Process 1. RX Interrupt is generated and Jumped to Interrupt Service Routine 2.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 15. Electrical Information 15.1 Absolute Maximum Ratings Symbol Parameter Min Max Unit VDD DC Supply Voltage -0.5 7.0 V VIN Input Voltage -0.5 VDD+0.5 V VOUT Output Voltage Range 0 VDD+0.5 V TSTG Storage Temperature -40 150 ℃ TOP Operating Temperature -40 85 ℃ Absolute maximum ratings are the values beyond which damage to the device may occur.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 16. Timing Specification 16.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 V_Th CLK V_test T_su V_Tl T_h V_Th INPUT V_test inputs valid V_test V_max V_Tl Figure 16-2: Input Timing Measurement Conditions Symbol 3.3V Signaling Units Vth 0.6Vcc V Vtl 0.2Vcc V Vtest 0.4Vcc V Vtrise 0.285Vcc V Vtfall 0.615Vcc V Vmax 0.4Vcc V 1.
SB16C1052PCI PCI Target Interface Controller with Dual UART JULY 2013 REV 1.06 17. Package Outline 128-Pin TQFP: Low-profile Quad Flat Package; Body 14ⅹ14ⅹ1.4 mm 0.23 0.13 1.45 MAX 1.60 MAX 0.10 0.4 14.0 16.0 0.75 0.45 0-7 1.00 Note : All dimensions are in millimeters.
