Datasheet

2-16
X7DBR-8/X7DBR-i User's Manual
®
S
UPER X7DBR-8/i
Fan1
8-pin PWR
FP Ctrl
IDE1
Floppy
SATA1
SATA0
USB2/3
SMB
Battery
North Bridge
20-pin ATX Main PWR
JPG1
SCSI
CTRLR
CPU1
South
Bridge
JAR
PWR
SMB
Fan2
Compact Flash
JCF1
JWF1
JL1
PCI-X 100MHz
USB4/5
WOL
DA1
DIMM 4A
DIMM 4B
KB
MS
USB0/1
COM1
GLAN2
GLAN1
JI
2
C1
E2x8
SXB-
VGA
SCSI Chann. B
JWD
SATA3
SATA2
SATA5
SATA4
Fan5
Fan4
Fan3
4-pin
PWR
3rd PWR
Fail
Buzzer
JPWF
Bank4
Bank3
E3x8
SXB-
JPL1
JPL2
JPA1
LVD/SE
U320
WOR
Chan A
U320 SCSI
JBT1
GLAN
CTRLR
VGA
CTRLR
BIOS
DA2
DIMM 3A
DIMM 3B
DIMM 2A
DIMM 2B
Bank2
Bank1
DIMM 1A
DIMM 1B
CPU2
SIMSO
COM2
PCI-X 100MHz ZCR SXB- E2x8
JI
2
C2
PWLED SPK
LE1
JOH1
J7
DA7
SGPIO1
SGPIO2
S I/O
JPA2
JPA3
Fan Headers
The X7DBR-8/X7DBR-i has fi ve chassis/sys-
tem fan headers (Fan1 to Fan5.) See the table
on the right for pin defi nitions. (*The onboard
fan speeds are controlled by Thermal Manage-
ment via BIOS Hardware Monitoring in the
Advanced Setting
. Note: Default: Disabled.)
(*Note: all these fans are 4-pin fan connec-
tors. However, Pins 1-3 of the fan headers
are backward compatible with the traditional
3-pin fans.)
3-Pin Fan Header
Pin Defi nitions
Pin# Defi nition
1 Ground
2 +12V
3 Tachometer
B
C
E
D
A
A. Fan 1
B. Fan 2
C. Fan 3
D. Fan 4
E. Fan 5
4-Pin Fan Header
Pin Defi nitions
Pin# Defi nition
1 Ground
2 +12V
3 Tachometer
4 PWM Signals