Datasheet

2-10
X7DB8/X7DBE User's Manual
Power LED
The Power LED connection is located
on pins 15 and 16 of JF1. Refer to the
table on the right for pin defi nitions.
NMI Button
The non-maskable interrupt button
header is located on pins 19 and 20
of JF1. Refer to the table on the right
for pin defi nitions.
Power Button
OH/Fan Fail LED
1
NIC1 LED
Reset Button
2
HDD LED
Power LED
Reset
PWR
Vcc
Vcc
Vcc
Vcc
Ground
Ground
1920
Vcc
X
Ground
NMI
X
Vcc
PWR Fail LED
NIC2 LED
NMI Button
Pin Defi nitions (JF1)
Pin# Defi nition
19 Control
20 Ground
Power LED
Pin Defi nitions (JF1)
Pin# Defi nition
15 +5V
16 Ground
C. Front Control Panel Pin Defi nitions
A. NMI
B. PWR LED
A
B
GLAN1
®
JLAN1
S
U
P
E
R X7DB8
/
E
GLAN2
Fan1
8-pin PWR
FP Ctrl
SPK
PW LED
JOH1
Fan3
I
DE1
Flopp
y
BI
OS
320 SCSI Channel A
Fan4
SAT
A1
SAT
A0
US
B
2
/
3
SM
B
PCI-X 100
M
Hz
ZC
R
PCI-X 133 M
Hz
J
WD
B
atter
y
VG
A
P
C
I-E
x
p
x
8
Nort
h B
ridge
VG
A
COM
1
US
B
0
/
1
K
B
/
M
ouse
Fan
6
Fan
5
AT
X PWR
4
-Pin
PWR
J3P
Parrallel Port
24-Pin
J
PG
1
SCSI CTRL
CPU1
CPU2
S
outh
B
rid
g
e
P
X
H
DIMM 1A (Bank 1)
Fan
7
JAR
PSF
Fan2
C
ompact
Flash
L
E
1
Fan8
J
CF
1
J
WF1
J
PA2
J
P
A
3
J
PA
1
320 SCSI Channel B
SAT
A3
SAT
A2
SAT
A4
SAT
A5
J
L1
JK1
S
lot1
S
lot2
S
lot3
PCI-X 133 M
Hz
S
lot4
J
PL1
J
P
L
2
S
lot5
PCI-Exp x4
S
lot6
PCI-Exp x8
SEPC
SIMLP IPMI
S
lot7
DIMM
1B
(
Ban
k 1)
D
IMM 2A (Bank
2)
DI
MM
2B (Bank
2
)
DIMM
3A (Ban
k 3)
DIMM
3B (Bank
3)
DI
MM 4A (Ban
k 4)
DIMM
4
B
(Bank 4)
J
BT1
USB
4
JW
OR
J
COM2
D
A
2
WO
L
D
A
1
S
I
/O
JP1
LA
N
CT
R
L
J27
J28
S
GP
IO1
S
GP
IO2
SMB PS
CT
RL
J7