User`s manual
Chapter 2: Installation
2-27
IDE Connectors
There are no jumpers to
configure the onboard IDE#1
and #2 connectors (at J3
and J4, respectively). See
the table on the right for pin
definitions.
Pin Number Function
1 Reset IDE
3 Host Data 7
5 Host Data 6
7 Host Data 5
9 Host Data 4
11 Host Data 3
13 Host Data 2
15 Host Data 1
17 Host Data 0
19 GND
21 DRQ3
23 I/O W rite-
25 I/O Read-
27 IOCHRDY
29 DACK3-
31 IRQ14
33 Addr 1
35 Addr 0
37 Chip Select 0
39 Activity
Pin Number Function
2 GND
4 Host Data 8
6 Host Data 9
8 Host Data 10
10 Host Data 11
12 Host Data 12
14 Host Data 13
16 Host Data 14
18 Host Data 15
20 Key
22 GND
24 GND
26 GND
28 BALE
30 GND
32 IOCS16-
34 GND
36 Addr 2
38 Chip Select 1-
40 GND
IDE Connector Pin Definitions
GLAN1
®
S
U
P
E
R
X
6D
H
8-X
G
2
GLAN2
D
IM
M
2
B
(B
a
n
k
2
)
D
IM
M
2
A
(B
a
n
k
2
)
D
IM
M
3
B
(B
a
n
k
3
)
D
IM
M
3
A
(B
a
n
k
3
)
D
IM
M
4
B
(B
a
n
k
4
)
D
IM
M
4
A
(B
a
n
k
4
)
D
IM
M
1
A
(B
a
n
k
1
)
D
IM
M
1
B
(B
a
n
k
1
)
Fan1
8-pin
PWR
PWR
SMBus
CPU
Fan1
JF1
F
P
C
o
n
tr
o
l
JD1
S
P
K
PW LED
JP15
Fan2
OH
3rd PS
PWR
Fault
Detect
CPU Fan2
Fan3
CH Intru
JL1
W
D Enable
IPM
I
IDE1
ID
E
2
F
lo
p
p
y
BIO
S
J
1
8
JPA1
Ultra 320
S
C
S
I C
H
A
U
l
t
r
a
3
2
0
S
C
S
I
C
H
B
F
a
n
4
7902
C
TR
L
SATA0
SATA1
U
SB
2/3
SM
BU
S
Buzzer
P
C
I
-
X
1
1
0
0
M
H
z
Z
C
R
P
C
I
-
X
2
1
0
0
M
H
z
P
C
I
-
X
#
3
1
3
3
M
H
z
WOR
Battery
JPL1
G
LAN
CTLR
RA
GE-X
82546
G
LAN
Enable
P
C
I
-
X
#
5
1
3
3
M
H
z
X
8
P
C
I
-
E
p
x
#
6
Super
I/O
(North
B
ridge)
JPG
1
VGA
C
O
M
1
U
S
B
0/1
KB/
M
ouse
Fan5
Fan6
ATX PW
R
4-Pin
PW
R
JP16
24-Pin
Force PWR ON
VGA
Enable
Fan7
J24
J
P
1
2
Reboot
Option
JP14
JP
13
F
a
n
8
SCSI
CPU 1
CPU 2
A
la
rm
R
es
et
SCSI
Enable
PXH
P
C
I
-
X
#
4
1
3
3
M
H
z
CO
M
2
W
O
L
U
SB
4
P
W
R
Fault
LE1
PW
LED
JPA2
JPA
3
DA1
DA2
ICH5R
PXH
L
i
n
d
e
n
h
u
r
s
t
Clear
CMOS
CHB SCSI LED
CHA SCSI LED
(South
Bridge)
E7520
82801ER
SCSI CH A Term
SCSI CH B Term
IDE1
IDE2