User`s manual

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2-22

X6DH8-XG2/X6DHE-XG2 User's Manual

Watch Dog

J18 controls Watch Dog, a system

monitor that takes action when a

software application hangs. Close

Pins 1-2 to reset the system if a

program hangs. Close Pins 2-3 to

generate a non-maskable interrupt

for the program that hangs. Watch

Dog must also be enabled in BIOS.

Jumper

Position

Pins 1-2

Pins 2-3

Open

Definition

WD to Reset

WD to NMI

Disabled

Watch Dog

Jumper Settings (J18)

CMOS Clear

JBT1 is used to clear CMOS. In-

stead of pins, this "jumper" consists

of contact pads to prevent the acci-

dental clearing of CMOS. To clear

CMOS, use a metal object such as a

small screwdriver to touch both

pads at the same time to short the

connection. Always remove the AC

power cord from the system before

clearing CMOS.

Note: For an ATX power supply,

you must completely shut down the

system, remove the AC power cord

and then short JBT1 to clear CMOS.

Do not use the PW_ON connec-

tor to clear CMOS.

GLAN1

®

S

U

P

E

R

X

6D

H

8-X

G

2

GLAN2

DIMM 2B (Bank 2)

DIMM 2A (Bank 2)

DIMM 3B (Bank 3)

DIMM 3A (Bank 3)

DIMM 4B (Bank 4)

DIMM 4A (Bank 4)

DIMM 1A (Bank 1)

DIMM 1B (Bank 1)

Fan1

8-pin

PWR

PWR

SMBus

CPU

Fan1

JF1

F

P

C

o

n

tro

l

J

D

1

SPK

PW LED

JP15

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU Fan2

Fan3

CH Intru

JL1

WD Enable

IPMI

IDE1

IDE2

F

l

o

p

p

y

BIOS

J

1

8

JPA1

Ultra 320

S

C

S

I C

H

A

U

l

t

r

a

3

2

0

S

C

S

I

C

H

B

F

a

n

4

7902

CTRL

SATA0

SATA1

USB2/3

SMBUS

Buzzer

P

C

I

-

X

1

1

0

0

M

H

z

Z

C

R

P

C

I

-

X

2

1

0

0

M

H

z

P

C

I

-

X

#

3

1

3

3

M

H

z

W

O

R

Battery

JPL1

GLAN

CTLR

RAGE-X

82546

GLAN

Enable

P

C

I

-

X

#

5

1

3

3

M

H

z

X

8

P

C

I

-

E

p

x

#

6

S

u

p

e

r

I/O

(North

Bridge)

JPG1

VGA

COM1

USB0/1

KB/

Mouse

Fan5

Fan6

ATX PWR

4-Pin

PWR

JP16

24-Pin

Force PWR ON

VGA

Enable

Fan7

J24

J

P

1

2

R

e

b

o

o

t

O

p

t

i

o

n

JP14

J

P

1

3

Fan8

SCSI

CPU 1

CPU 2

A

l

a

r

m

R

e

s

e

t

SCSI

Enable

PXH

P

C

I

-

X

#

4

1

3

3

M

H

z

COM2

WOL

USB4

PWR

Fault

L

E

1

PW LED

JPA2

JPA3

DA1

DA

2

ICH5R

PXH

L

i

n

d

e

n

h

u

r

s

t

Clear

CMOS

CHB SCSI LED

CHA SCSI LED

(South

Bridge)

E

7

5

2

0

8

2

8

0

1

E

R

SCSI CH A Term

SCSI CH B Term

WD

Clear CMOS